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Digital Implementation

Applied Micro Circuits Sumbal Rafiq Applied Micro Circuits Sumbal Rafiq, Director of Engineering at Applied Micro Circuits, describes the success with the Cadence Encounter Digital Implementation System.

Celestial Semiconductor

Design Challenge
	Convert to a 0.13µm process while increasing the frequency to 220MHz
	Minimizing the impact of IR drop and signal integrity
	Tape out the chip in a very tight project schedule
Cadence Solution
	Cadence® Encounter® digital IC design platform
Read Full story »

Fujitsu Microelectronics

Design Challenge
	Align power design around CPF with accurate simulation
	Move to smaller geometries
	Reduce design time and improve QoS
Cadence Solution
	Integrated, proven design solution leverages success in new applications
	Accurate verification of final design improves silicon
Read Full story»

Global Unichip Corporation (GUC) Albert Li Global Unichip Corporation (GUC) Albert Li, Director of Design and Development at Global Unichip Corporation, outlines the benefits of partnering with Cadence for giga-gate/GHz, 28nm design.

NEC video Martin Spohr NEC video Martin Spohr, Senior Engineer, NEC Electronics from NEC Video talks about using Encounter Conformal Constraint Designer to overcome nanometer design challenges.

nVidia Bruce Cory nVidia Bruce Cory, DFT Methodology Manager from nVidia talks about the importance of test coverage and how Cadence Encounter Test delivered quality in several situations.

NVIDIA Chris Malachowsky NVIDIA Chris Malachowsky, VP of Engineering from NVIDIA talks about the challenges of dealing with 90 and 65 nanometer technologies, and how Cadence technologies and partnering approach help NVIDIA get results.

P.A. Semi Amit Chandra P.A. Semi Amit Chandra, Sr. Engineering Manager of P.A. Semi talks about using the Encounter platform to overcome high-performance, low power design challenges.

P.A. Semi Dan Dobberpuhl P.A. Semi Dan Dobberpuhl, President and CEO of P.A. Semi talks about using the Encounter platform to overcome high-performance, 65nm design design challenges.

Renesas Martin Spohr Renesas Martin Spohr, Principal Design Engineer Design Services at Renesas Electronics Europe describes the benefits of using the Cadence Encounter Digital Implementation System post assembly closure methodology to ensure design closure on their complex giga-gate design.

Renesas

Design Challenge
	Process variation causes performance/yield tradeoffs
	Implement SSTA without huge memory and processing time requirements
Cadence Solution
	Encounter Timing System with SSTA - Very fast, accurate and does not require large work space - Tightly integrated with other Encounter capabilities
Read Full story»

Sonics Frank Ferro Sonics Frank Ferro, Director of Marketing, describes the success with the Cadence Encounter Digital Implementation System.

Teledyne

Design Challenge
	Performing metal-only ECO changes on derivative products had grown time-consuming and cost-prohibitive
	Imager chip project scope included ECO modifications to eight different functional blocks—which could not be supported with existing manual ECO flow
	Engineering team had concerns about maintaining quality while meeting project’s stringent timeline requirements
Cadence Solution
	Cadence Encounter Conformal ECO Designer
Read Full story»

TSMC North America David Lan TSMC David Lan, Senior Manager, Design Methodology from TSMC North America collaborates with Cadence to offer 90-nanometer design solutions to its customers.

ZMD Thilo von Selchow ZMD Thilo von Selchow, CEO from ZMD talks about how ZMD and Cadence Engineering Services work together to produce cutting-edge ZigBee wireless solutions.

Freescale Semiconductor Anis Jarrar Freescale Semiconductor Anis Jarrar, Principal Design Engineer, at Freescale Semiconductor describes how they utilized the Cadence Low-Power Solution to design and implement the complex Kinetis SoC.

Technical University of Braunschweig

Challenges
	Prepare students for workforce by teaching with powerful electronic design automation (EDA) technologies
	Cultivate relationships with educators and corporations to further academic research in low-power digital design
Cadence Solutions
	Cadence Academic Network
	Incisive Unified Simulator
	Encounter RTL Compiler
	Encounter Digital Implementation System
	3D Design Viewer
	C-to-Silicon Compiler
Results
	Students earn internships and jobs at leading technology companies with a strong presence in Europe
	TUBS participates in publicly funded research projects involving low-power digital design
Read Full story»

Texas Instruments Ty Garibay Texas Instruments Ty Garibay, Director of IC Engineering for OMAP platform business unit at Texas Instruments describes how they leveraged Cadence unified digital flow to develop SoCs for mobile applications productively, profitably, and quickly.

Triune Systems

Ross Teggatz
Triune Systems
Ross Teggatz, President/Founder at Triune Systems outlines the values of using the Cadence unified digital and unified custom/analog flows to meet their mixed-signal design requirements and close time to market gaps.