Home > Tools > Digital Implementation > Customer Success

Digital Implementation 

Applied Micro Circuits
Sumbal Rafiq
Applied Micro Circuits

Sumbal Rafiq, Director of Engineering at Applied Micro Circuits, describes the success with the Cadence Encounter Digital Implementation System.

ARM
Brent McKanna
ARM

Brent McKanna, ARM® principal design engineer and implementation tech lead for the ARM Cortex®-A57 processor, discusses how the collaboration between his company and Cadence will benefit designers of enterprise and high-end mobile applications. Using Cadence® tools, including the Encounter® platform, ARM got the right topologies on critical paths of the processor, while hitting frequency goals and staying below power and area goals. Watch the video to learn more about reference methodology scripts created by ARM and Cadence to give design engineers a jump start on development with the Cortex-A5 processor.

ARM, Samsung and Cadence
ARM, Samsung and Cadence
Dipesh Patel, EVP and GM, Physical IP Division at ARM, Ana Hunter, VP of Foundry at Samsung Semiconductor and Chi-Ping Hsu, SVP, R&D at Cadence discuss the collaboration between the three companies to develop the first 14nm, FinFET implementation of the ARM Cortex A7.

Avago
Jack Benzel
Expert Engineer at Avago Technologies
Jack Benzel, Expert Engineer at Avago Technologies, describes how the new GigaOpt technology in Encounter Digital Implementation (EDI) System boosts IC design quality.

Avago Technologies
Jason Gentry
Avago Technologies

In this video from CDNLive Silicon Valley 2014, Jason Gentry, master IC design engineer for ASIC products division at Avago Technologies, describes how he used the Cadence® Encounter® digital implementation system's command line interface to add his own route-planner script and Encounter's multi-partition functionality to split the design into more levels of hierarchy. By doing so, Avago completed top-level route and timing closure in a lot less time—hours instead of days or weeks—because they were working on smaller pieces of the design in parallel.

Celestial Semiconductor
Design Challenge
Convert to a 0.13µm process while increasing the frequency to 220MHz
Minimizing the impact of IR drop and signal integrity
Tape out the chip in a very tight project schedule

Cadence Solution
Cadence® Encounter® digital IC design platform
 Read Full story »

Faraday
Business Challenge
Consistently provide highly differentiated ASIC, SoC, and IP designs to customers while achieving lower cost and faster time to market
Design Challenges
Automate the functional ECO process (including bug fixes and new feature introductions/deletions)
Minimize the risk of quality issues and schedule slips
Cadence Solution
Encounter Conformal ECO Designer
Results
Achieved faster functional ECO implementation turnaround time by minimizing manual work and timeconsuming iterations
Gained the ability to implement complex ECOs, a task nearly impossible using the traditional manual process
Achieved earlier netlist handoff to customers
Reduced manufacturing costs and accelerated time to market for customers
 Read Full story»

Fujitsu Microelectronics
Design Challenge
Align power design around CPF with accurate simulation
Move to smaller geometries
Reduce design time and improve QoS

Cadence Solution
Integrated, proven design solution leverages success in new applications
Accurate verification of final design improves silicon
 Read Full story»

Global Unichip Corporation (GUC)
Albert Li
Global Unichip Corporation (GUC)

Albert Li, Director of Design and Development at Global Unichip Corporation, outlines the benefits of partnering with Cadence for giga-gate/GHz, 28nm design.

NEC video
Martin Spohr
NEC video

Martin Spohr, Senior Engineer, NEC Electronics from NEC Video talks about using Encounter Conformal Constraint Designer to overcome nanometer design challenges.

nVidia
Bruce Cory
nVidia

Bruce Cory, DFT Methodology Manager from nVidia talks about the importance of test coverage and how Cadence Encounter Test delivered quality in several situations.

NVIDIA
Chris Malachowsky
NVIDIA

Chris Malachowsky, VP of Engineering from NVIDIA talks about the challenges of dealing with 90 and 65 nanometer technologies, and how Cadence technologies and partnering approach help NVIDIA get results.

P.A. Semi
Amit Chandra
P.A. Semi

Amit Chandra, Sr. Engineering Manager of P.A. Semi talks about using the Encounter platform to overcome high-performance, low power design challenges.

P.A. Semi
Dan Dobberpuhl
P.A. Semi

Dan Dobberpuhl, President and CEO of P.A. Semi talks about using the Encounter platform to overcome high-performance, 65nm design design challenges.

Renesas
Martin Spohr
Renesas

Martin Spohr, Principal Design Engineer Design Services at Renesas Electronics Europe describes the benefits of using the Cadence Encounter Digital Implementation System post assembly closure methodology to ensure design closure on their complex giga-gate design.

Renesas
Design Challenge
Process variation causes performance/yield tradeoffs
Implement SSTA without huge memory and processing time requirements

Cadence Solution
Encounter Timing System with SSTA
- Very fast, accurate and does not require large work space
- Tightly integrated with other Encounter capabilities
 Read Full story»

Sharp
Business Challenge
Speed a new CMOS image sensor’s time to market without sacrificing product quality
Design Challenge
Address timing and routability convergence challenges
Cadence Solutions
Encounter RTL-to-GDSII flow
Encounter RTL Compiler
Encounter Conformal Equivalence Checker
Encounter Digital Implementation System
Encounter Test
Results
2x improvement in turnaround time
Higher quality results in timing, area, and productivity
 Read Full story»

Silicon Labs
Business Challenge
  • Ramp up the company’s product development capabilities
Design Challenge
  • Create and implement efficient design flow and methodology, supported by single toolset, for development of low-energy MCUs
Cadence Solution
  • Integrated mixed-signal, low-power RTLto-signoff flow based on Cadence Assura, Encounter, Incisive, and Virtuoso platforms
Results
  • Saved several months in development time for design flows
  • 20 months after the start-up of the company, the first 32-bit MCU (EFM32 Gecko) was launched, consuming only a quarter of the energy of competing products
  • Developed new 32-bit MCU in just 4 months, saving up to 8 months of effort due to innovative design methodology and focus on re-usability
 Read full story»

Sonics
Frank Ferro
Sonics

Frank Ferro, Director of Marketing, describes the success with the Cadence Encounter Digital Implementation System.

Sound Design
Design Challenge
Develop the industry’s first monolithic, 4-core audio aid
Shrink the die size to meet a 3.8mm limit for the human ear
Meet ultra-low power targets with customized clock timing and advanced chip stacking

Cadence Solution
Provide a complete, production-proven, advanced digital design, implementation, and verification flow
Mitigate risk and optimize time to productivity with expert design consulting services
 Read Full story»

ST Microelectronics
Business Challenge
  • Get automotive semiconductor products to market quickly, while adapting to frequently changing customer specifications
Design Challenge
  • Automate RTL ECOs for pre- and post-mask layouts
Cadence Solution
  • Encounter Conformal ECO Designer
Results
  • 4 months average estimated savings in product development time
  • Significant mask-cost savings per design
  • Up to 30% productivity gain for design engineers
 Read full story»

Teledyne
Design Challenge
Performing metal-only ECO changes on derivative products had grown time-consuming and cost-prohibitive
Imager chip project scope included ECO modifications to eight different functional blocks—which could not be supported with existing manual ECO flow
Engineering team had concerns about maintaining quality while meeting project’s stringent timeline requirements

Cadence Solution
Cadence Encounter Conformal ECO Designer
 Read Full story»

Texas Instruments
Business Challenges
Deliver the best application processor with optimal performance, power consumption, and thermal conditions
Limit power consumption within two watts
Design Challenges
Provide accurate power estimation based on real use cases
Develop a methodology and a power dashboard, and continually track power updates
Achieve close correlation between an architect’s power estimation and actual silicon measurement
Cadence Solutions
Palladium XP Dynamic Power Analysis
Encounter Power System
Results
Power estimation and actual silicon measurement at 96% accuracy
Detected unexpected power peaks and resolved design to lower power consumption
 Read Full story»

TSMC North America
David Lan
TSMC

David Lan, Senior Manager, Design Methodology from TSMC North America collaborates with Cadence to offer 90-nanometer design solutions to its customers.

Uniquify
Business Challenge
Remain competitive by achieving 100% tapeout success in increasingly short timeframes
Design Challenges
Meet aggressive performance, power, and cost goals
Perform comprehensive physical design space exploration and feasibility analysis early in the design process
Cadence Solutions
Encounter Digital Implementation (EDI) System
QRC Extraction
Results
In combination with Uniquify’s design methodology, Perseus, Cadence has helped Uniquify achieve:
25%-30% faster design closure
Faster time to design, leading to faster time to market
Greater efficiency, translating into lower costs
High levels of quality
 Read Full story»

ZMD
Thilo von Selchow
ZMD

Thilo von Selchow, CEO from ZMD talks about how ZMD and Cadence Engineering Services work together to produce cutting-edge ZigBee wireless solutions.

Faraday Technology
Business Challenge
  • Produce prototype of highly complex, 300-million-gate SoC—the 1st such effort in Taiwan—in 7 months
  • Grow business through ability to develop large-scale chip designs
Design Challenges
  • Shorten verification and analyses processes
  • Process large database for huge SoC design
  • Manage and integrate different technologies across industries
Cadence Solutions
  • First Encounter® Design Exploration and Prototyping
  • Encounter® Digital Implementation System
  • Encounter Conformal® Equivalence Checker
  • Incisive® verification platform
  • Sigrity™ packaging and PCB signal and power analysis solutions
  • Verification IP Catalog
Results
  • Completed complex design from data-in to tapeout within 7 months
  • Reduced one iteration for timing optimization, extraction, analysis and verification of physical design down to 4 days
  • Expanded design capacity by 10X
 Read full story»

Freescale Semiconductor
Angela Liang
Freescale Semiconductor

Hear from Angela Liang, Sr. Mixed-Signal Verification Engineer, at Freescale Semiconductor as she describes how they utilized the Cadence Low Power and Mixed-Signal Solution to verify the company’s Kinetis Microcontroller products targeted for automotive and internet-of-things applications.

Freescale Semiconductor
Anis Jarrar
Freescale Semiconductor
Anis Jarrar, Principal Design Engineer, at Freescale Semiconductor describes how they utilized the Cadence Low-Power Solution to design and implement the complex Kinetis SoC.

Freescale Semiconductor
Nikhil Murgai
Freescale Semiconductor

Routing and timing closure were big challenges on the high-performance cores developed by Freescale Semiconductor. How did the engineers improve these processes? Watch this video to hear Nikhil Murgai, lead design engineer at Freescale Semiconductor, talk about how the team used Cadence® Encounter® digital implementation tools to save routing resources and speed up the timing closure process.

Global Unichip
Albert Li
Global Unichip

Watch this video for insights into Global Unichip's successful tapeout of a 20nm testchip with Cadence and TSMC. Albert Li, marketing director at Global Unichip, talks about the collaborative effort and overcoming advanced node challenges such as double patterning and new design rules.

GLOBALFOUNDRIES
Luigi Capodieci
GLOBALFOUNDRIES

Luigi Capodieci, Director of Design for Manufacturing, R&D Fellow at GLOBALFOUNDRIES, discusses how they collaborated with Cadence on pattern-matching technologies to accelerate full-chip DFM signoff.

IBM
Lars Liebman
IBM

Lars Liebman, Distinguished Engineer at IBM, highlights the collaboration between IBM and Cadence in solving design challenges at 20nm and 14nm technology nodes.

imec
Antoine Dejonghe
Program Manager
imec
Antoine Dejonghe, Green Radio Program Manager at imec, highlights the use of the Cadence CPF-Driven Advanced Low-Power Solution that accelerates the company’s next generation 4G wireless designs.

MegaChips
Suryansh Sahota
MegaChips

MegaChips found that its traditional ECO methodology was not producing the results needed. In this video, Suryansh Sahota, a design engineer at the company, talks about how a physically aware ECO methodology based on Cadence's Tempus™ Timing Signoff Solution and Encounter® Digital Implementation System yielded far better TAT, power consumption, and elimination of DRV, setup, and hold violations.

MegaChips
Designing a networking chip with a hierarchical design can be very challenging in terms of timing correlation between synthesis and implementation and congestion after scan insert. Raghavendra Prasad, a senior design engineer at MegaChips, talks about how much measurable improvement the company gained by applying physically aware synthesis with Cadence® Encounter® RTL Compiler with Physical. Watch the video to learn how to avoid surprises in layout.

Nvidia
Santosh Navale
Nvidia

Designed for applications including tablets, smartphones, gaming cards, and supercomputers, Nvidia's high-performance, advanced-node application processors have stringent power and performance requirements and complex clocking schemes. In this video, Santosh Navale, a physical design engineer at Nvidia, talks about how Cadence® Encounter® Digital Implementation System CCOpt technology has improved concurrent datapath and clock optimization, the timing closure process, and overall chip performance. With CCOpt technology, Nvidia has been able to meet its tough design goals.

Open-Silicon
Tilak Miryala
Open-Silicon

Open-Silicon develops complex chips with millions of gates, thousands of clocks, as well as repeatable blocks. Timing signoff and constraints validation can be quite challenging. Tilak Miryala, a design engineer at the company, talks about the limitations of a traditional ECO flow, the advantages of a traditional physically aware ECO flow, and, finally, the benefits of an MC-ECO flow available in the Cadence® Encounter® Digital Implementation System and Tempus™ Timing Signoff Solution.

Open-Silicon, Inc.
Shrikrishna Mehetre and Souvik Mazmunder
Open-Silicon, Inc.

Hear from Shrikrishna Mehetre and Souvik Mazmunder, with Open-Silicon, Inc., as they highlight the use of Cadence Encounter digital RTL-to-signoff products to achieve 2.2 GHz performance on a 28nm ARM Dual-Core Cortex-A9 processor.

S3
S3
Flavio Cali

Hear from Flavio Cali with S3 Group, as he highlights the user experience of Cadence Physical Verification System (PVS) for SoC design.

Technical University of Braunschweig
Challenges
Prepare students for workforce by teaching with powerful electronic design automation (EDA) technologies
Cultivate relationships with educators and corporations to further academic research in low-power digital design
Cadence Solutions
Cadence Academic Network
Incisive Unified Simulator
Encounter RTL Compiler
Encounter Digital Implementation System
3D Design Viewer
C-to-Silicon Compiler
Results
Students earn internships and jobs at leading technology companies with a strong presence in Europe
TUBS participates in publicly funded research projects involving low-power digital design
 Read Full story»

Texas Instruments
Ty Garibay
Texas Instruments

Ty Garibay, Director of IC Engineering for OMAP platform business unit at Texas Instruments describes how they leveraged Cadence unified digital flow to develop SoCs for mobile applications productively, profitably, and quickly.

Triune Systems
Ross Teggatz
Triune Systems

Ross Teggatz, President/Founder at Triune Systems outlines the values of using the Cadence unified digital and unified custom/analog flows to meet their mixed-signal design requirements and close time to market gaps.

TSMC
Maria Marced
TSMC Europe

Maria Marced, President of TSMC Europe, discusses with Christian Malter, Director Technology Solutions, EMEA, Cadence, the significance of 16nm FinFET technology and highlights their collaboration with Cadence.

TSMC
Maria Marced
TSMC Europe

Maria Marced, President of TSMC Europe, and Christian Malter, Director Technology Solutions, EMEA, Cadence, discuss how customers benefit from the collaboration between the two companies in the mixed-signal space.

VIA Telecom
Business Challenge
  • Deliver low-power baseband processors in a highly competitive market
  • Meet customers’ increasingly aggressive product development cycles
Design Challenges
  • Automate manual process for verifying power intent of processor designs
Cadence Solutions
  • Encounter Conformal Low Power
  • Encounter Digital Implementation System
  • Encounter RTL Compiler
  • Incisive Enterprise Simulator
Results
  • 30% faster product development process
  • Ability to take on 25% more projects with same resource level, which translates into new business for the company
  • Ability to achieve first silicon success
 Read full story»