Built on a patented graph-based architecture, Cadence® NanoRoute® Advanced Digital Router combines the performance characteristics of a grid-based router with the flexibility of an off-grid router. It takes an already placed gate-level netlist and generates a tapeout-ready GDSII design database.
With its second-generation, patent-awarded
SMART2 technology—a concurrent and unified
Signal integrity,
Manufacturing
Aware,
Routing, and
Timing optimization system—NanoRoute Router holistically addresses timing, area, power, signal integrity, and manufacturability constraints during physical implementation. Its remarkable speed and capacity comes from its patent-awarded graph-based architecture coupled with its superthreading technology, which combines multi-threading and parallel-processing techniques. The result is a fast routing solution that can handle all aspects of routing the most complex multimillion-gate designs at both block and chip levels.
Features/Benefits
- Delivers an all-purpose digital routing solution for top-level and block-level routing
- Enhances productivity through efficient single-CPU and multi-CPU performance, resulting in 10x or more performance gain
- SMART2 routing and superthreading technology deliver superior quality of results and rapid design closure
- Handles mainstream and advanced process technology nodes, from 130nm and older to 32/28nm.
- Automated prevention and fixing reduces litho errors by up to 80% with minimal additional runtime, memory, or changes to route topology
- Integrates with Cadence Encounter® Digital Implementation System