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First Encounter Design Exploration and Prototyping 


Eliminate implementation iterations and late-cycle design surprises

First Encounter technology enables quick full-chip virtual prototyping to accurately capture downstream physical/electrical impacts at the beginning of the design cycle. Its unique partitioning and budgeting capabilities combined with GigaFlex Abstraction Technology makes hierarchical implementation easier and faster for giga-scale, high-speed designs.

First Encounter Design Exploration and Prototyping Datasheet »
10 resources found
 
Title Type Rated
First Encounter Design Exploration and Prototyping Datasheet
Format: .PDF    Date: 30 Apr 2013
Datasheet
 7
Recommend!
Package Effect on Chip Power Supply: Can Designers Afford to Ignore It?
Format: .PDF (4.6MB)    Date: 15 Sep 2007
Conference Paper
 1
Recommend!
Yield Aware Design Flows for 90 and below
Format: .PDF (1.4MB)    Date: 15 Apr 2007
Conference Paper
 4
Recommend!
Real Design Challenges of Low-Power Physical Implementation
Format: .PDF (4.3MB)    Date: 15 Apr 2007
Conference Paper
 1
Recommend!
Using Advanced Low-power Techniques to Mitigate Headaches, an interview
Format: .PDF    Date: 29 Jan 2007
Cadence Article
 0
Recommend!
Cadence Encounter Digital IC Design Demo: Necessary and Absolute Signoff Analysis for 65/45nm Design
Date: 29 Jan 2007
Demo
 15
Recommend!
An Innovative Flow to Implement Large Scale Design Changes in the Final Stages of Physical Implementation
Format: .PDF    Date: 29 Oct 2006
Conference Paper
 0
Recommend!
Using First Encounter and VoltageStorm to Optimize Peak IR drop or Power Mesh Area
Format: .PDF    Date: 21 Sep 2006
Conference Paper
 0
Recommend!
Power Grid Analysis of Low Power Designs with Coarse/Fine Grain Power Gates
Format: .PDF    Date: 20 Jul 2006
Application Note
 2
Recommend!
Cadence Encounter Digital IC Design Platform Brochure
Format: .PDF    Date: 01 Apr 2005
Brochure
 20
Recommend!