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First Encounter Design Exploration and Prototyping 

Eliminate implementation iterations and late-cycle design surprises

First Encounter technology enables quick full-chip virtual prototyping to accurately capture downstream physical/electrical impacts at the beginning of the design cycle. Its unique partitioning and budgeting capabilities combined with GigaFlex Abstraction Technology makes hierarchical implementation easier and faster for giga-scale, high-speed designs.

First Encounter Design Exploration and Prototyping Datasheet »

Product Image Accommodating today’s chip design requirements within narrow market windows has led to a predictability crisis. How can engineers determine design feasibility for larger, higher-performance, power-hungry chips with an incomplete netlist, library, and constraints? And how can they quickly assess floorplans for congestion, timing, and power without having to go into real implementation?

First Encounter technology addresses these challenges and more. It spans silicon virtual prototyping, automatic floorplanning, physical synthesis, hierarchical controls for partitioning and budgeting, legal macro and standard cell placement, complete power-grid design and optimization, and hierarchical clock synthesis for high-performance, complex 100M+ instance designs. With such comprehensive capabilities, First Encounter technology helps customers meet their time-to-market requirements confidently, and with significant performance and productivity gains.

Predictability and convergence
  • Enables early design exploration and accurate chip feasibility analysis
  • Performs automated floorplan synthesis and ranking for a flexible, predictable path to design closure
Productivity and faster time to market
  • FlexModels and FlexILM abstraction technology adapts to the flow, providing the right mix of capacity and accuracy, enabling designers to achieve up to 20x improvements in capacity and turnaround time
  • Partition-in-partition technology natively manages multi-level hierarchical designs
  • Supports hierarchical methodologies such as bottom-up block-based flows, top-down black-box flows, and hybrid flows for 100M+ instance designs
  • Provides a unified flow for partitioning, pin assignment, macro placement, feedthrough insertion, pipeline registers, clock planning, and time budgeting
  • Delivers intuitive and visual global timing, power, and clock debug and diagnostics features
Ease of use
  • Integrates design flows and common engines from the front-end, implementation, and packaging domains
  • Delivers a ready-to-use prototyping foundation flow with design exploration to get to an implementation-ready floorplan
Product differentiation and lower cost
  • Supports concurrent chip/package design and optimization
  • Supports integrated automatic area and peripheral I/O placement and optimization
  • Supports flip-chip RDL routing capabilities