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First Encounter Design Exploration and Prototyping 


Eliminate implementation iterations and late-cycle design surprises

First Encounter technology enables quick full-chip virtual prototyping to accurately capture downstream physical/electrical impacts at the beginning of the design cycle. Its unique partitioning and budgeting capabilities make hierarchical implementation easier and faster for large-scale, high-speed designs.

First Encounter Design Exploration and Prototyping Datasheet »

Product Image As geometries shrink and the design sizes of complex SoC systems increase, the technical challenges now associated with achieving silicon success are many. How do you determine design feasibility of these larger, higher-performance, power-hungrier chips with incomplete netlists, libraries, and constraints? How can you quickly assess floorplans for congestion, timing, and power before going into real implementation? And how do you effectively partition a huge design to have minimal impact on turnaround time and design schedules?

Plan to succeed with Cadence® First Encounter® technology. Its comprehensive design planning, analysis, and debug capabilities provide a continuous convergent path and boost predictability and efficiency in your design flow. First Encounter technology spans RTL and physical synthesis, silicon virtual prototyping, automatic floorplanning, hierarchical partitioning and budgeting, legal macro and standard cell placement, complete power-grid design and optimization, and hierarchical clock synthesis for the latest high-performance, high-complexity designs. These capabilities help customers eliminate late-cycle surprises and implementation iterations so they can meet their time-to-market requirements confidently and with significant performance and productivity gains.

Benefits
Predictability and convergence
  • Enables design exploration and accurate chip feasibility analysis (including automated floorplan synthesis and ranking) for a flexible and predictable path to design closure
Productivity and faster time to market
  • Supports robust and flexible hierarchical methodologies, including bottom-up block-based flows, top-down black-box flows, and hybrid flows with partitioning, time budgeting, and innovative top-level assembly and optimization technologies
  • Offers signoff-driven implementation and intuitive and visual global timing, power, and clock debug and diagnostics features
Ease of use
  • Provides continuous convergence and ease of use through integrated design flows and common engines among front-end, implementation, and packaging stages
  • Prototyping foundation flow enables ready-to-use solution with design exploration to achieve an implementation-ready floorplan
Differentiated products with lower total development costs
  • Supports concurrent design and optimization of chip and package with integrated automatic area and peripheral I/O placement and optimization, plus flip-chip RDL routing capabilities
  • Links into Cadence InCyte Chip Estimator to enable architectural prototyping, which reduces risk for system architects and closes the gap between system and implementation worlds