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Encounter Timing System 


Unified timing analysis for faster design closure and signoff

Encounter® Timing System tightly couples the design implementation environment with the timing signoff environment. This improves timing convergence throughout the design flow and greatly reduces the time to design closure. As a complete standalone solution, Encounter Timing System offers silicon-accurate timing signoff and signal integrity analysis that ensures operational chips after tapeout.

Encounter Timing System Datasheet »
11 resources found
 
Title Type Rated
Cadence and Renesas Success Story
Format: .PDF    Date: 11 Jul 2012
Success Story
 13
Recommend!
Cadence and NetEffect Success Story
Format: .PDF    Date: 11 Jul 2012
Success Story
 1
Recommend!
Encounter Timing System Datasheet
Format: .PDF (1.4MB)    Date: 16 Feb 2012
Datasheet
 19
Recommend!
Validation and Debugging of Statistical Analysis - Key to Robustness of Cadence SSTA solution
Format: .PDF    Date: 15 Sep 2007
Conference Paper
 0
Recommend!
Interview: Making Reliable Models for SSTA
Format: .PDF    Date: 10 Sep 2007
Cadence Article
 0
Recommend!
Interview: Freescale's Alex Albuerne uses Encounter Timing System to Overcome Timing Challenges
Format: .PDF    Date: 03 Aug 2007
Cadence Article
 3
Recommend!
Common Platform Datasheet for Cadence 65nm Low-Power Reference Flow
Format: .PDF    Date: 01 Jul 2007
Datasheet
 5
Recommend!
Cadence Encounter Digital IC Design Demo: Necessary and Absolute Signoff Analysis for 65/45nm Design
Date: 29 Jan 2007
Demo
 15
Recommend!
Designing Out DFM Issues at 65 nm
Format: .PDF (2.1MB)    Date: 27 Jun 2006
Conference Paper
 1
Recommend!
Fast and Accurate Statistical Cell Characterization with Spectre
Format: .PDF    Date: 04 Apr 2006
Conference Paper
 0
Recommend!
Cadence Encounter Digital IC Design Platform Brochure
Format: .PDF    Date: 01 Apr 2005
Brochure
 20
Recommend!