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Encounter Power System 

Unified power analysis for faster design optimization and signoff

Encounter® Power System enables accurate and high-capacity power analysis, helping designers debug and verify that power and IR drop constraints are met across multimillion-gate designs and multiple die—with significant gains in productivity. Integrated with Encounter Digital Implementation System to improve design convergence, it is part of a complete Cadence signoff solution that includes Encounter Timing System and Encounter Library Characterizer.

Encounter Power System Datasheet »

Product Image Encounter Power System enables design teams to accurately validate distributed power consumption, IR drop, power rail electromigration, and signal net electromigration (wire self-heat) for complex designs manufactured on all technology nodes. When used with Encounter Digital Implementation System, Encounter Power System enables automated power-rated optimizations driven by analysis results, which improves productivity for design teams.

Encounter Power System is built on production-proven, signoff-quality algorithms and engines that have been used to validate thousands of successful tapeouts. It provides a comprehensive static and dynamic power integrity analysis and signoff solution, combining high performance, capacity, and accuracy with best-in-class debugging capabilities.

Used throughout the design implementation flow, Encounter Power System enables early floor- and power-planning, together with signoff analysis and optimizations for block implementation, chip-level assembly, and pre-tapeout signoff. Using signoff-quality engines throughout the design flow enables consistent, convergent results at every step.

Designed for optimal usability, it has the flexibility to rapidly check that the power rails can supply the amount of power needed during floorplanning, while also enabling accurate, silicon-validated signoff to verify that blocks and the full chip do not suffer from power-related issues.

Encounter Power System drives multiple optimizations to fix power integrity issues, including power rail and via array sizing, size/location of de-coupling capacitance, size/location of power switches, and I/O placement. It reports all components of power consumption and graphically shows areas of high dynamic power caused by simultaneously switching logic.

Encounter Power System’s power calculation engine enables Verilog-based, early gate-level power estimations as well as signoff-accurate distributed power calculation. It leverages Encounter Timing System’s signoff timing engine for accurate slew and timing windows needed during vectorless dynamic power calculation.

For power-switch optimization, Encounter Power System can be used to tune the number of power switches while reporting if high rush current could cause local IR drop. The combination of Encounter Timing System and Encounter Power System delivers a comprehensive clock and signal jitter/skew analysis solution. To enable accurate chip/package co-design, Encounter Power System accepts package loading models and outputs a die model of the chip that drives package design and analysis.

  • Delivers consistent, integrated power and IR drop analysis across the implementation flow, from floorplanning through optimization and signoff
  • Provides a unified signoff analysis solution
  • Performs comprehensive, hierarchical full-chip and package IR drop analysis
  • Boosts productivity and shaves weeks off tapeout schedules
  • Allows easy debugging
  • Offers advanced power analysis capabilities
  • Supported by major foundries, ASIC and IP vendors, and integrated device manufacturers
* Encounter Power System is the next generation VoltageStorm Power Verification.