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Encounter Power System 


Unified power analysis for faster design optimization and signoff

Encounter® Power System enables accurate and high-capacity power analysis, helping designers debug and verify that power and IR drop constraints are met across multimillion-gate designs and multiple die—with significant gains in productivity. Integrated with Encounter Digital Implementation System to improve design convergence, it is part of a complete Cadence signoff solution that includes Encounter Timing System and Encounter Library Characterizer.

Encounter Power System Datasheet »
6 resources found
 
Title Type Rated
Texas Instruments and Cadence Verification Customer Success Story
Format: .PDF    Date: 14 Dec 2012
Success Story
 5
Recommend!
Building Energy-Efficient ICs from the Ground Up White Paper
Format: .PDF    Date: 10 Oct 2012
White Paper
 3
Recommend!
Encounter Power System Datasheet
Format: .PDF (1MB)    Date: 31 Jan 2012
Datasheet
 5
Recommend!
Cadence and Sound Design Technologies Success Story
Format: .PDF    Date: 19 Apr 2010
Success Story
 3
Recommend!
Fujitsu’s CPF Based Low Power Design Status and Today’s Power Format Conference Paper
Format: .PDF    Date: 20 May 2009
Conference Paper
 6
Recommend!
Cadence Encounter Digital IC Design Demo: Necessary and Absolute Signoff Analysis for 65/45nm Design
Date: 29 Jan 2007
Demo
 15
Recommend!