Cadence® Encounter® Power System offers designers a complete and accurate view of distributed on-chip power consumption , IR drop, power rail electromigration, and thermal analysis. It delivers the utmost in productivity, precision, and performance for the most complex advanced node designs.
Encounter Power System and its native production-proven VoltageStorm® signoff engines have been in use for more than a decade with thousands of successful tapeouts for both analysis and in-design optimization. It is used across the implementation flow, spanning floorplanning, power planning, design optimization, and signoff to provide consistent, converging results at every step of the flow. Encounter Power System helps front-end logic designers looking for high-quality early rail analysis and ease of use, as well as back-end physical designers looking for comprehensive signoff analysis and silicon correlation.
Encounter Power System supports low-power design methodologies with decoupling capacitance and power switch optimizations. Power ramp-up analysis enables power switch optimization to minimize rush currents on power-up while enabling an efficient power-up time.
For chip/package co-design, the Encounter Power System creates a die model that can be used to optimize package design, and accepts package loading information for accurate on-chip analysis.
Encounter Power System is available in L and XL configurations. An Encounter Power System Advanced Analysis Option is also available.
Features/Benefits
- Comprehensive analysis including static, dynamic, vector-driven, and vectorless approaches
- Full Common Power Format (CPF) support
- Consistent, integrated power and IR drop analysis across the implementation flow, from floorplanning through optimization and signoff
- Early power estimation with full RTL and gate-level VCD and SAIF support
- VCD profiling for easy identification of the most sensitive power vectors
- Efficient multi-mode analysis for design with multiple operating modes
- Multi-CPU enabled, with threaded and distributed processing
- Integrated with Encounter Timing System for access to timing database for accurate power analysis, and study of IR drop induced delay variability
- Integration with Encounter Timing System for a comprehensive clock jitter solution
- Integration with Encounter Digital Implementation System for ease-of-use during analysis execution and ECO fixing
- Comprehensive, hierarchical full-chip analysis using power grid views of analog, mixed-signal, custom digital, or full digital blocks for true full-chip IR drop analysis
- Chip/package co-design support through package and die model exchange with Cadence Allegro® Package Designer
- Increased productivity with full GUI-driven flows, interactive Tcl command interface, global power debug, and integrated waveform and physical viewers
- Full-chip thermal analysis
- Easy library generation using industry-standard LVS rule decks and Spice® sub-circuits
Encounter Power System is the next generation VoltageStorm Power Verification.