High-capacity, high-performance implementation of mainstream and advanced node designsA complete solution for variation- and manufacturing-aware design closure, low power, mixed-signal implementation, and integrated signoff in a single, scalable multi-CPU-enabled design environment.  Encounter Digital Implementation System Datasheet » |
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 Extending the production-proven Encounter technologies that designers trust, Encounter Digital Implementation System refines and advances digital design and implementation. It provides a focused, high-performance, advanced design closure solution for both flat and hierarchical designs while also addressing the latest requirements for low-power, mixed-signal, and advanced node design, including new 32 /28nm requirements. By supporting RTL synthesis, silicon virtual prototyping, design planning, and full-chip digital implementation and signoff in a single environment, Encounter Digital Implementation System gives engineers an early, accurate view of design feasibility and allows them to progress immediately to full-scale implementation and final signoff for large-scale, complex designs—without ever leaving the solution environment. Encounter Digital Implementation System is the next generation of SoC Encounter RTL-to-GDSII System.
BenefitsEnhanced productivity
- Enables rapid design closure on large-scale, high-performance, complex designs
- Offers ultra-large capacity and scalable performance with end-to-end, multi-CPU parallel processing
- Supports mainstream and advanced low-power and mixed-signal designs within a single environment
- Supports all advanced process technology nodes including new 32/28nm design requirements
- Enables chip/package co-design, analysis, and optimization, including 3D IC, multiple flip-chip methodologies, RDL routing, and silicon-in-packaging
Better predictability
- Combines RTL synthesis, design exploration, silicon virtual prototyping, full in-design signoff, and DFM/yield analysis and optimization
- Enables one-pass convergence to achieve the highest quality of silicon and eliminate schedule delays
- Foundation flows provide proven and consistent methodologies that are easy to adopt for fast and predictable production ramp-up
Increased profitability
- Widespread foundry and ecosystem support increases yield and lowers manufacturability risk
- Enables differentiated end products (multi-core, high performance, high utilization, flip-chip, 3D IC, and more)
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