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Designing with Silicon-on-Insulator (SOI) Technology 

Silicon-on-Insulator (SOI) technology offers some compelling benefits over traditional bulk CMOS technologies, which is why many chip makers are giving it a closer look. These benefits include higher chip performance per watt, smaller die size, and better scalability at smaller geometries over traditional process technologies.

As a result of deep collaboration with technology partners including ARM and IBM, Cadence is ready for SOI technology and committed to making it easy for designers to adopt. Cadence provides the only production-proven, end-to-end design solution and methodology available for implementation and verification of analog, digital, and mixed-signal SOI IP blocks and SoCs. Just use Cadence tools like you normally do for bulk process in your existing production design flow.

Technologies
  • Cadence Virtuoso platform enables analog and custom digital design, implementation, and verification of SOI designs and IP
  • Cadence Encounter family of products enables implementation and signoff of your SOI-based designs and IP
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