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Digital Implementation

Applied Micro Circuits Sumbal Rafiq Applied Micro Circuits Sumbal Rafiq, Director of Engineering at Applied Micro Circuits, describes the success with the Cadence Encounter Digital Implementation System.

Celestial Semiconductor

Design Challenge
	Convert to a 0.13µm process while increasing the frequency to 220MHz
	Minimizing the impact of IR drop and signal integrity
	Tape out the chip in a very tight project schedule
Cadence Solution
	Cadence® Encounter® digital IC design platform
Read Full story »

Fujitsu Microelectronics

Design Challenge
	Align power design around CPF with accurate simulation
	Move to smaller geometries
	Reduce design time and improve QoS
Cadence Solution
	Integrated, proven design solution leverages success in new applications
	Accurate verification of final design improves silicon
Read Full story»

NEC video Martin Spohr NEC video Martin Spohr, Senior Engineer, NEC Electronics from NEC Video talks about using Encounter Conformal Constraint Designer to overcome nanometer design challenges.

NemeriX

Design Challenge
	Achieve the lowest possible power consumption for new GPS chipset
	Complete back-end process for complex design in two months
Cadence Solution
	Deployed the Cadence Encounter® digital IC design platform low-power flow using Virage ultra-high-density (UHD) libraries to address both front- and back-end design challenges
	Trained NemeriX engineering team on best practices for future designs
Read Full story »

nVidia Bruce Cory nVidia Bruce Cory, DFT Methodology Manager from nVidia talks about the importance of test coverage and how Cadence Encounter Test delivered quality in several situations.

nVidia Chris Malachowsky nVidia Chris Malachowsky, VP of Engineering from nVidia talks about the challenges of dealing with 90 and 65 nanometer technologies, and how Cadence technologies and partnering approach help nVidia get results.

P.A. Semi Amit Chandra P.A. Semi Amit Chandra, Sr. Engineering Manager of P.A. Semi talks about using the Encounter platform to overcome high-performance, low power design challenges.

P.A. Semi Dan Dobberpuhl P.A. Semi Dan Dobberpuhl, President and CEO of P.A. Semi talks about using the Encounter platform to overcome high-performance, 65nm design design challenges.

Renesas

Design Challenge
	Process variation causes performance/yield tradeoffs
	Implement SSTA without huge memory and processing time requirements
Cadence Solution
	Encounter Timing System with SSTA - Very fast, accurate and does not require large work space - Tightly integrated with other Encounter capabilities
Read Full story»

Sonics Frank Ferro Sonics Frank Ferro, Director of Marketing, describes the success with the Cadence Encounter Digital Implementation System.

TSMC North America David Lan TSMC David Lan, Senior Manager, Design Methodology from TSMC North America collaborates with Cadence to offer 90-nanometer design solutions to its customers.

ZMD

Thilo von Selchow

ZMD
Thilo von Selchow, CEO from ZMD talks about how ZMD and Cadence Engineering Services work together to produce cutting-edge ZigBee wireless solutions.