Home > Products > Digital Implementation > Customer Success

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Company Location *

Comments: *

Send Yourself A Copy

Digital Implementation

Applied Micro Circuits Sumbal Rafiq Applied Micro Circuits Sumbal Rafiq, Director of Engineering at Applied Micro Circuits, describes the success with the Cadence Encounter Digital Implementation System.

ARM, Samsung and Cadence ARM, Samsung and Cadence Dipesh Patel, EVP and GM, Physical IP Division at ARM, Ana Hunter, VP of Foundry at Samsung Semiconductor and Chi-Ping Hsu, SVP, R&D at Cadence discuss the collaboration between the three companies to develop the first 14nm, FinFET implementation of the ARM Cortex A7.

Celestial Semiconductor

Design Challenge
	Convert to a 0.13µm process while increasing the frequency to 220MHz
	Minimizing the impact of IR drop and signal integrity
	Tape out the chip in a very tight project schedule
Cadence Solution
	Cadence® Encounter® digital IC design platform
Read Full story »

Faraday

Business Challenge
	Consistently provide highly differentiated ASIC, SoC, and IP designs to customers while achieving lower cost and faster time to market
Design Challenges
	Automate the functional ECO process (including bug fixes and new feature introductions/deletions)
	Minimize the risk of quality issues and schedule slips
Cadence Solution
	Encounter Conformal ECO Designer
Results
	Achieved faster functional ECO implementation turnaround time by minimizing manual work and timeconsuming iterations
	Gained the ability to implement complex ECOs, a task nearly impossible using the traditional manual process
	Achieved earlier netlist handoff to customers
	Reduced manufacturing costs and accelerated time to market for customers
Read Full story»

Fujitsu Microelectronics

Design Challenge
	Align power design around CPF with accurate simulation
	Move to smaller geometries
	Reduce design time and improve QoS
Cadence Solution
	Integrated, proven design solution leverages success in new applications
	Accurate verification of final design improves silicon
Read Full story»

Global Unichip Corporation (GUC) Albert Li Global Unichip Corporation (GUC) Albert Li, Director of Design and Development at Global Unichip Corporation, outlines the benefits of partnering with Cadence for giga-gate/GHz, 28nm design.

NEC video Martin Spohr NEC video Martin Spohr, Senior Engineer, NEC Electronics from NEC Video talks about using Encounter Conformal Constraint Designer to overcome nanometer design challenges.

nVidia Bruce Cory nVidia Bruce Cory, DFT Methodology Manager from nVidia talks about the importance of test coverage and how Cadence Encounter Test delivered quality in several situations.

NVIDIA Chris Malachowsky NVIDIA Chris Malachowsky, VP of Engineering from NVIDIA talks about the challenges of dealing with 90 and 65 nanometer technologies, and how Cadence technologies and partnering approach help NVIDIA get results.

P.A. Semi Amit Chandra P.A. Semi Amit Chandra, Sr. Engineering Manager of P.A. Semi talks about using the Encounter platform to overcome high-performance, low power design challenges.

P.A. Semi Dan Dobberpuhl P.A. Semi Dan Dobberpuhl, President and CEO of P.A. Semi talks about using the Encounter platform to overcome high-performance, 65nm design design challenges.

Renesas Martin Spohr Renesas Martin Spohr, Principal Design Engineer Design Services at Renesas Electronics Europe describes the benefits of using the Cadence Encounter Digital Implementation System post assembly closure methodology to ensure design closure on their complex giga-gate design.

Renesas

Design Challenge
	Process variation causes performance/yield tradeoffs
	Implement SSTA without huge memory and processing time requirements
Cadence Solution
	Encounter Timing System with SSTA - Very fast, accurate and does not require large work space - Tightly integrated with other Encounter capabilities
Read Full story»

Sharp

Business Challenge
	Speed a new CMOS image sensor’s time to market without sacrificing product quality
Design Challenge
	Address timing and routability convergence challenges
Cadence Solutions
	Encounter RTL-to-GDSII flow
	Encounter RTL Compiler
	Encounter Conformal Equivalence Checker
	Encounter Digital Implementation System
	Encounter Test
Results
	2x improvement in turnaround time
	Higher quality results in timing, area, and productivity
Read Full story»

Sonics Frank Ferro Sonics Frank Ferro, Director of Marketing, describes the success with the Cadence Encounter Digital Implementation System.

Sound Design

Design Challenge
	Develop the industry’s first monolithic, 4-core audio aid
	Shrink the die size to meet a 3.8mm limit for the human ear
	Meet ultra-low power targets with customized clock timing and advanced chip stacking
Cadence Solution
	Provide a complete, production-proven, advanced digital design, implementation, and verification flow
	Mitigate risk and optimize time to productivity with expert design consulting services
Read Full story»

Teledyne

Design Challenge
	Performing metal-only ECO changes on derivative products had grown time-consuming and cost-prohibitive
	Imager chip project scope included ECO modifications to eight different functional blocks—which could not be supported with existing manual ECO flow
	Engineering team had concerns about maintaining quality while meeting project’s stringent timeline requirements
Cadence Solution
	Cadence Encounter Conformal ECO Designer
Read Full story»

Texas Instruments

Business Challenges
	Deliver the best application processor with optimal performance, power consumption, and thermal conditions
	Limit power consumption within two watts
Design Challenges
	Provide accurate power estimation based on real use cases
	Develop a methodology and a power dashboard, and continually track power updates
	Achieve close correlation between an architect’s power estimation and actual silicon measurement
Cadence Solutions
	Palladium XP Dynamic Power Analysis
	Encounter Power System
Results
	Power estimation and actual silicon measurement at 96% accuracy
	Detected unexpected power peaks and resolved design to lower power consumption
Read Full story»

TSMC North America David Lan TSMC David Lan, Senior Manager, Design Methodology from TSMC North America collaborates with Cadence to offer 90-nanometer design solutions to its customers.

Uniquify

Business Challenge
	Remain competitive by achieving 100% tapeout success in increasingly short timeframes
Design Challenges
	Meet aggressive performance, power, and cost goals
	Perform comprehensive physical design space exploration and feasibility analysis early in the design process
Cadence Solutions
	Encounter Digital Implementation (EDI) System
	QRC Extraction
Results
	In combination with Uniquify’s design methodology, Perseus, Cadence has helped Uniquify achieve:
	25%-30% faster design closure
	Faster time to design, leading to faster time to market
	Greater efficiency, translating into lower costs
	High levels of quality
Read Full story»

ZMD Thilo von Selchow ZMD Thilo von Selchow, CEO from ZMD talks about how ZMD and Cadence Engineering Services work together to produce cutting-edge ZigBee wireless solutions.

Freescale Semiconductor Anis Jarrar Freescale Semiconductor Anis Jarrar, Principal Design Engineer, at Freescale Semiconductor describes how they utilized the Cadence Low-Power Solution to design and implement the complex Kinetis SoC.

GLOBALFOUNDRIES Luigi Capodieci GLOBALFOUNDRIES Luigi Capodieci, Director of Design for Manufacturing, R&D Fellow at GLOBALFOUNDRIES, discusses how they collaborated with Cadence on pattern-matching technologies to accelerate full-chip DFM signoff.

IBM Lars Liebman IBM Lars Liebman, Distinguished Engineer at IBM, highlights the collaboration between IBM and Cadence in solving design challenges at 20nm and 14nm technology nodes.

imec Antoine Dejonghe Program Manager imec Antoine Dejonghe, Green Radio Program Manager at imec, highlights the use of the Cadence CPF-Driven Advanced Low-Power Solution that accelerates the company’s next generation 4G wireless designs.

Open-Silicon, Inc. Shrikrishna Mehetre and Souvik Mazmunder Open-Silicon, Inc. Hear from Shrikrishna Mehetre and Souvik Mazmunder, with Open-Silicon, Inc., as they highlight the use of Cadence Encounter digital RTL-to-signoff products to achieve 2.2 GHz performance on a 28nm ARM Dual-Core Cortex-A9 processor.

Technical University of Braunschweig

Challenges
	Prepare students for workforce by teaching with powerful electronic design automation (EDA) technologies
	Cultivate relationships with educators and corporations to further academic research in low-power digital design
Cadence Solutions
	Cadence Academic Network
	Incisive Unified Simulator
	Encounter RTL Compiler
	Encounter Digital Implementation System
	3D Design Viewer
	C-to-Silicon Compiler
Results
	Students earn internships and jobs at leading technology companies with a strong presence in Europe
	TUBS participates in publicly funded research projects involving low-power digital design
Read Full story»

Texas Instruments Ty Garibay Texas Instruments Ty Garibay, Director of IC Engineering for OMAP platform business unit at Texas Instruments describes how they leveraged Cadence unified digital flow to develop SoCs for mobile applications productively, profitably, and quickly.

Triune Systems

Ross Teggatz
Triune Systems
Ross Teggatz, President/Founder at Triune Systems outlines the values of using the Cadence unified digital and unified custom/analog flows to meet their mixed-signal design requirements and close time to market gaps.