 | Physical Verification System
System accelerates design signoff by orders
of magnitude compared to conventional tools. It facilitates multiple design turns per day for large 90nm and 65nm designs. Performance scales linearly and is limited only by the compute resources available.
|
| Virtuoso AMS Silicon Analysis
Verifies that a physical layout meets manufacturing rules and matches the intended schematic. Extracts parasitic resistance and capacitance values from a layout for use in circuit simulations and analyzes power nets in analog layouts to detect risk of failures due to IR drop and electromigration on power nets
|
| Virtuoso AMS-HF Silicon Analysis
In addition to the capabilities of Virtuoso AMS Silicon Analysis, provides the ability to extract inductance values from a layout for use in circuit simulations and analyze power and signal nets to detect risk of electromigration failures
|
| Assura Design Rule Checker
Supports both interactive and batch operation modes and utilizes hierarchical processing to identify and correct design rule errors
|
| Assura Layout vs. Schematic
Ensures that the layout connectivity of the physical design matches the logical design represented by the schematic or netlist before tapeout. Extracts devices and nets formed across layout hierarchy and compares them to the schematic netlist
|
| Assura Parasitic Extraction
Provides parasitic extraction on full-chip layouts with silicon accuracy
|
| Diva Physical Verification
Provides real-time physical verification of cells, blocks, and small IC designs
|
| Virtuoso Analog VoltageStorm Option
An option to the Virtuoso Analog Design Environment. Extends the VoltageStorm family of power integrity products to analog designs
|
| Virtuoso Analog ElectronStorm Option
An option to the Virtuoso Analog Design Environment. Addresses electromigration validation for analog designs
|
| PacifIC Static Noise Analyzer
Analyzes the combined impact of major noise sources including crosstalk, IR drop, and propagated noise on custom digital designs
|
