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Cadence Physical Verification System

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The Cadence® Physical Verification System (PVS) is the premier Cadence solution for SoC signoff.

PVS offers competitive single-processor and distributed-processor performance, sufficient for high-end SoC designs implemented in advanced process nodes. With 100% file compatibility and ease of use, PVS is a drop-in replacement for existing physical verification technologies.

PVS is a proven product, with many users and successful production tapeouts in nanometer process technologies.

Key benefits


Delivers a single-vendor solution for implementation and back-end signoff
Speeds design turnaround with production-proven accuracy
Simplifies migration through direct compatibility with industry-standard formats
Accelerates debug cycle through integration with Virtuoso® and Encounter® technologies


The Cadence Physical Verification System integrates with industry-standard design flows and formats
The Cadence Physical Verification System integrates with industry-standard design flows and formats


What's new

Addressing manufacturing variation at advanced nodes
Applying silicon-coutour-based DFM is important as designers move into 45nm designs and beyond.

SPIE and the IC design world: a wall starts coming down
SPIE Advanced Lithography 2008 recently showed how much the wall between SoC design and chip manufacturing has come down.

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