Cadence design for manufacturing (DFM) technologies enable you to verify and optimize layouts in digital and custom IC designs, while providing a reliable way to achieve manufacturing sign-off before tape-out.
To successfully get nanometer-scale designs to market, semiconductor companies must address a
growing array of challenges—from ever-more stringent design rules to increasing chip layout
complexity. Designers must also contend with the physical effects that become much more troublesome
at these smaller geometries. Lithographical and CMP manufacturing effects can have significant
impact on both functional and parametric yield. Process variations across the die, wafer, and
batch affect yield, performance, and reliability.
Cadence recognizes these challenges and has created the most comprehensive Design for
Manufacturing (DFM) solutions in the industry. Cadence technologies are integrated into
design flows to prevent manufacturing effects from impacting digital and custom layouts,
analyze systematic and random variability on designs and optimize the design to maximize
yield. In minimizing the impact of random and systematic manufacturing effects on functional
and parametric yield, Cadence provides designers with the technologies and flows they
need to address the industry's most difficult DFM challenges.
