Design for manufacturing
Cadence Kits
Incisive functional verification
Encounter digital IC design
Virtuoso custom design
Allegro IC-PKG-PCB co-design
OrCAD PCB design
System-in-package design
Design for manufacturing
PRODUCTS
Assura DRC
Assura LVS
Cadence CMP Predictor
Cadence Litho Electrical Analyzer
Cadence Litho Physical Analyzer
Cadence MaskCompose Suite
Cadence QRC Extraction
Diva Physical Verification
Dracula
Encounter Test
Physical Verification System
DESIGN TASKS
Silicon analysis
Analysis and signoff
IP catalog
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Design for Manufacturing design tasks
Silicon analysis
Silicon analysis is an integral part of in the Virtuoso custom design platform that allows designers to perform physical verification, parasitic extraction, substrate noise modeling, signal and power integrity analysis to ensure that designs are functional and manufacturable on silicon. Silicon analysis promotes both physical and electrical signoff before tapeout.
Analysis and signoff
The Digital Implementation solution delivers the most comprehensive and accurate analysis and signoff solution. It brings together logical, physical, electrical, and manufacturing domain requirements in a single, easy-to-use environment, enabling front-end to back-end design handoff, signoff-driven implementation, and final signoff.