Cadence Kits
Incisive functional verification
Encounter digital IC design
Virtuoso custom design
Allegro IC-PKG-PCB co-design
OrCAD PCB design
System-in-package design
Design for manufacturing
PRODUCTS
Assura DRC
Assura LVS
Cadence CMP Predictor
Cadence Litho Electrical Analyzer
Cadence Litho Physical Analyzer
Cadence MaskCompose Suite
Cadence QRC Extraction
Diva Physical Verification
Dracula
Encounter Test
Physical Verification System
DESIGN TASKS
Silicon analysis
Analysis and signoff
IP catalog
Print-friendly version
COSMIC

COSMIC™ was launched in 1998 as an open-source test-chip measurement methodology standard for interconnect extraction verification. With COSMIC as a standard, foundries and EDA companies can eliminate redundant test chips and supply accurate extraction validation results to their customers. COSMIC enables companies to use one test chip to validate all extractors to a higher degree of accuracy than ever before, and save the time and money previously wasted due to lack of standardization.

Cadence uses the COSMIC methodology on test chips with leading foundries to validate that Fire & Ice® QXC full-chip 3D extraction tool is within /-10% of silicon.

Feel free to view the COSMIC test structures. If you would like to use them in your own test chip or validation process, complete the registration form, read and sign the license agreement and then download the structures, which are provided in GDSII format.

COSMIC is an "active" approach to measuring capacitance at the femtofarad level (one femtofarad is equal to 0.001 picofarad), as it uses an on-chip sensor circuit for the measurements. It is based on research originally performed at UC Berkeley, which was then enhanced to produce COSMIC.

Since its inception for total capacitance measurement of Al metal lines, the COSMIC approach has been extended to measure capacitance for Cu metal lines in 130nm process and lower technology nodes. In addition to the total capacitance, the enhanced methodology now can also measure the coupling capacitance between any two lines in the presence of any other lines. The new methodology has been patented (US Patent 5999010).

Earlier approaches, known as "passive," measured semiconductors only to the picofarad range, which is insufficient for the microscopic scale of deep submicron wires. Cadence is the first company to successfully validate extraction accuracy using an active test chip methodology.