ASSURA LAYOUT vs. SCHEMATIC VERIFIER Assura™ Layout vs. Schematic (LVS) Verifier is part of the design verification suite of tools within the Virtuoso® custom design platform. Assura LVS ensures that the layout connectivity of the physical design matches the logical design represented by the schematic or netlist before tapeout by automatically extracting devices and nets formed across layout hierarchy and comparing them to the schematic netlist. Assura LVS provides fast, efficient verification in both interactive and batch mode. Key benefits
Simplifies design process with a common database for data transfer within the Virtuoso custom design platform
Accelerates design-to-volume with production-proven interactive LVS debugger
Reduces re-spins by eliminating connectivity and mismatch errors before tapeout
Ensures success in analog mixed-signal design with support of mixed netlist and special devices
