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Virtuoso RF Designer

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Cadence® Virtuoso® RF Designer delivers a comprehensive EM simulation and verification solution that is tightly integrated into the Virtuoso custom design platform. It reduces iterations between layout and schematic by simultaneously considering electrical and physical effects.

Comprising a planar 3D, method of moments (MoM) electromagnetic (EM) solver, Virtuoso RF Designer models planar structures, components, and geometries typically found in RFICs, PCBs, and in SiPs. Virtuoso RF Designer accounts for a variety of parasitic effects throughout the design cycle, with the goal of reducing silicon spins through the use an EM solver. It also allows engineers to model a broad array of structures, along with the high-frequency effects found in RF/wireless designs.

Computational capabilities unique to Virtuoso RF Designer allow engineers to tackle physically larger designs that can extend from the component level to the entire cell, and complete them in much less time. It then returns S-parameter results that can be utilized in SPICE, RF, and mixed-signal simulators.

Key benefits


Reduces silicon spins through accurate full-wave EM simulation of a broad array of structures and interconnects
Speeds time to market by reducing the number of design iterations
Shortens learning curve and reduces errors in back annotating modeled data through tight integration into the Virtuoso custom design platform
Increases productivity by eliminating the need for standalone EM solvers
Ability to model physically large problems; no dividing designs into smaller components
Accurate modeling of sub-micron features such as thick metal, fills, and slots
Frequency support to 1Hz mitigating the need to extrapolate the DC points, hence, impacting circuit DC operating point


What's new

Addressing manufacturing variation at advanced nodes
Applying silicon-coutour-based DFM is important as designers move into 45nm designs and beyond.

SPIE and the IC design world: a wall starts coming down
SPIE Advanced Lithography 2008 recently showed how much the wall between SoC design and chip manufacturing has come down.

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