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Virtuoso RET Suite

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The days of "what you see on the layout is what you see on the wafer" are gone. The Virtuoso Resolution Enhancement Technique (RET) Suite brings lithography aware capabilities to the Cadence Virtuoso custom design platform.

The Virtuoso RET Suite is a collection of capabilities—including silicon imagers, LRC (litho rule checking) verifiers, and an assortment of interactive RET methods—that enable designers to securely and seamlessly run all the litho-related information and capabilities within the design environment.

Key benefits


Reduces the risk of litho-related respins by creating a "litho clean" design
Allows specific wafer fab capabilities to be brought seamlessly and securely to the design environment
Improves the speed and efficiency of the subsequent batch insertion and DRC steps
Reduces time to market and increases predictability through a litho-aware design process


Below 130nm, what you draw is not what you get
Below 130nm, what you draw is not what you get


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What's new

Addressing manufacturing variation at advanced nodes
Applying silicon-coutour-based DFM is important as designers move into 45nm designs and beyond.

SPIE and the IC design world: a wall starts coming down
SPIE Advanced Lithography 2008 recently showed how much the wall between SoC design and chip manufacturing has come down.

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