Cadence Design Systems, Inc.

Technical Info

This page contains technical information related to Custom IC design, including application notes, white papers, and articles.

White papers

	Using Parasitic-Aware Simulation in the Design and Verification of Complex RF SiP Modules

	Chip Design Using 45nm Processes Requires a Holistic Approach to Planning and Implementation

	AMD/Clear Shape: Automated Full-Chip Hotspot Detection and Removal Flow for Interconnect Layers of Cell-Based Designs

	Virtuoso UltraSim Full-Chip Simulator Netlist-Based EMIR Flow

	Specification-driven Design Environment is Key to Productivity Gains in Analog Design

more white papers

Articles

05/01/08	Toward a standard deep sub-micron analog design flow: Cadence enhances the Virtuoso Platform

04/29/08	Cadence offers new custom IC design capabilities

03/06/08	Is it really a black art or just a red herring?

06/18/07	Extraction Tool Makes Grade On TSMC's 45-nm Process

04/12/07	Efficient Computing and Advanced Visualization Accelerates Electronic Design

more articles

Cadence feature stories

07/11/07	Cadence Integrates SiP Technologies Into Latest Custom and Digital Design Flows

04/06/07	Cadence Space-Based Router Wins 17th Annual EDN Innovation Award for Best IC Back-End and DFM Product

09/22/06	CDNLive! Silicon Valley 2006 - Proof that analog and digital do mix

02/10/06	Virtuoso RET Suite Integrates Lithography Awareness Into Industry-Leading Layout Environment

02/02/06	Cadence Develops Advanced Manufacturing-Aware Chip Optimization Technology