Silicon analysis allows designers to perform physical verification, parasitic extraction, substrate noise modeling, signal and power integrity analysis to ensure that designs are functional and manufacturable on silicon. Silicon analysis promotes both physical and electrical signoff before tapeout.
Assura Design Rule Checker Supports both interactive and batch operation modes and utilizes hierarchical processing to identify and correct design rule errors
Assura Layout vs. Schematic Ensures that the layout connectivity of the physical design matches the logical design represented by the schematic or netlist before tapeout. Extracts devices and nets formed across layout hierarchy and compares them to the schematic netlist
Virtuoso Analog VoltageStorm Option An option to the Virtuoso Analog Design Environment. Extends the VoltageStorm family of power integrity products to analog designs
Virtuoso Analog ElectronStorm Option An option to the Virtuoso Analog Design Environment. Addresses electromigration validation for analog designs
