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Home > Products > Virtuoso custom design > Products > Cadence QRC Extraction
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Cadence QRC Extraction
As process nodes shrink, interconnect behavior dominates overall chip performance. Furthermore, the integration of fast switching digital and analog design blocks introduces additional challenges for designers. In this environment, a comprehensive parasitic extraction solution that addresses all design styles and advanced manufacturing effects becomes a key requirement to the design of reliable products.
Production-proven and independent of design style or flow, Cadence® QRC Extraction is the industry's premier 3D full-chip parasitic extractor for fast and accurate implementation and validation of complex designs. Its seamless integration with the Encounter® and Virtuoso® platforms offers designers an easy-to-use solution for rapid analysis to achieve faster timing closure and higher quality of silicon. Cadence QRC Extraction includes a full spectrum of technologies for all nanometer-scale design styles including RF, analog, mixed-signal, custom digital, and cell. These advanced capabilities include RLCK extraction, advanced process modeling, multi-corner and statistical extraction, distributed processing, netlist reduction, substrate parasitics extraction, an integrated field solver, and hierarchical extraction.
Cadence QRC Extraction offers capabilites of both Assura RCX  and Fire & ICE QX .
Key benefits
 | Reduces risk of re-spins with accurate, full-chip extraction | | Increases ROI with first-time accurate and consistent setup for all design styles | | Shortens design cycles by integrating with comprehensive design and analysis environments | | Speeds convergence for timing closure by integrating with analysis technologies |
| Key components of Cadence QRC Extraction |
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