Full-chip integration provides a solid floorplan of the entire design. Knowing where the blocks will fall helps designers address hot spots and sensitive wires that occur in most submicron designs. A combination of manual and automated tools seems to work best for this stage of custom design—where designers are likely to use synthesis, standard cell P&R and custom placement techniques for critical blocks. After placement, designers can move forward with routing, paying particular attention to multiple power and ground lines in the design. Final I/O placement and bump matrix generation and assignment can be optimized to ensure package routability and overall device timing and signal integrity performance as a co-design task in conjunction with the IC package designer.
Cadence Chip Optimizer Cadence® Chip Optimizer is silicon-proven, full-chip physical design optimization system that improves manufacturability, yield, and performance. It addresses today's requirements for shorter time to convergence and time to volume. Cadence Chip Optimizer works seamlessly with the Cadence Encounter® digital IC design platform and the Virtuoso® custom design platform.
Virtuoso Chip Editor Provides editing for full-chip finishing tasks and the capacity to handle your largest designs. It is fully interoperable with Encounter digital IC design platform and leverages the Virtuoso Layout Editor environment and infrastructure
Allegro Package Designer 620
IC package co-design system that enables I/O planning and bump matrix virtual prototyping with the Virtuoso custom design platform
Virtuoso Digital Implementation Option
The Cadence Virtuoso Digital Implementation Option is a complete synthesis and place-and-route system for small digital block implementation in context of analog-driven, mixed-signal design methodology
