Virtuoso custom design
Cadence Kits
Incisive functional verification
Encounter digital IC design
Virtuoso custom design
PRODUCTS
Virtuoso platform L
Virtuoso platform XL
Virtuoso platform GXL
Virtuoso Multi-Mode Simulation
Virtuoso AMS Designer Simulator
Virtuoso Spectre Circuit Simulator
Virtuoso UltraSim Full-chip Simulator
Virtuoso Layout Migrate
Virtuoso Digital Implementation
Virtuoso RET Suite
Virtuoso RF Designer
Cadence Chip Optimizer
Cadence Space-Based Router
Cadence QRC Extraction
Virtuoso Analog ElectronStorm Option
Virtuoso Analog VoltageStorm Option
Virtuoso Passive Component Designer
Assura DRC
Assura LVS
Cadence SiP RF Layout
Cadence SiP RF Architect
Other Virtuoso Products
DESIGN TASKS
Advanced device modeling
Specification-driven design
Multi-mode simulation
Accelerated layout
Silicon analysis
Full-chip integration
RF SiP Design
Allegro IC-PKG-PCB co-design
OrCAD PCB design
System-in-package design
Design for manufacturing
IP catalog
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Virtuoso custom design platform design tasks
Specification-driven design
Each design starts with a set of specifications—measurements and goals—that need to be achieved by the chip. In a specification-driven environment, these measurements and goals are captured in a central location where the design response can be checked against them anytime during the design process. A specification-driven environment helps to manage late design changes that may require quick re-creation of all of the measurements and re-simulation of the modified design.
Multi-mode simulation
Simulation allows designers to test their design. However, design IP comes in many variations. Depending on the design stage, behavioral models might be used for some blocks, while others are at the transistor level—or even contain extracted parasitics from layout. Multi-mode simulation addresses these variations in design IP to show the signal response of the design quickly and accurately—regardless of how the design is defined.
Accelerated physical layout
Once the design creation and simulation have been completed, the design moves on to the physical layout stage. Proper technologies can help automate and accelerate the cell placement and metal routing. For custom IC design, tools that allow a combination of direct interaction—for specific layout needs—and automation—for speed—support accelerated physical layout.
Silicon analysis
Silicon analysis allows designers to perform physical verification, parasitic extraction, substrate noise modeling, signal and power integrity analysis to ensure that designs are functional and manufacturable on silicon. Silicon analysis promotes both physical and electrical signoff before tapeout.
Full-chip integration
Full-chip integration provides a solid floorplan of the entire design. Knowing where the blocks will fall helps designers address hot spots and sensitive wires that occur in most submicron designs. A combination of manual and automated tools seems to work best for this stage of custom design—where designers are likely to use synthesis, standard cell P&R and custom placement techniques for critical blocks. After placement, designers can move forward with routing, paying particular attention to multiple power and ground lines in the design.