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Home > Products > Virtuoso custom design > Demos

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Custom IC design demos and webinars

This page contains demonstrations and webinars related to the Virtuoso custom design platform.

Demonstrations



Advanced Virtuoso Design Environment (IC 6.1 release)

Accelerated Physical Design with Virtuoso Prototype Flow (IC 6.1 release)

Virtuoso Constraint Flow (IC 6.1 release)

Solving D/MS Design Challenges with Virtuoso AMS Designer (5.1.41)

Solving New Challenges in Nanometer Design with Assura™ Physical Verification (3.1)


Webinars



04/08/08Circuit Simulation-Driven Analog/RF System-in-Package Webinar Series: Top-Down Design and Circuit Simulation of Analog/RF Systems-in-Package Using Virtuoso and SiP RF Solutions
01/24/08Circuit Simulation-Driven Analog/RF System-in-Package Webinar Series: Advanced Techniques for IC Package/SiP Parasitic Extraction/Modeling and Backannotation for Circuit Simulation Using Virtuoso ADE and SiP RF
12/13/07Circuit Simulation-Driven Analog/RF System-in-Package Webinar Series: Designing Off-Chip IC Package/SiP-Level Passive Structures Using Virtuoso and SiP RF Technology
11/15/07Circuit Simulation-Driven Analog/RF System-in-Package Webinar Series: Circuit Simulation of Analog/RF ICs with IC Package Interconnect Using Virtuoso ADE and SiP RF
10/25/07Archived Webinar: Circuit Simulation-Driven Analog/RF System-in-Package Webinar Series: Interfacing With the IC Package Design Team Using Virtuoso and SiP RF Architect
09/06/07Archived Webinar: Circuit-Simulation-Driven RF/Analog System-In-Package Design
06/28/07Archive Webinar: Cadence Simulation & Verification Webinar Series - Accurate Verification of Next-Generation Custom Digital SoC and Memories in 65/45nm Technologies
06/26/07Archived Webinar: Cadence Simulation & Verification Webinar Series - Verification of Next-Generation Wireless SoC and Systems in Package
06/21/07Archived Webinar: Cadence Simulation & Verification Webinar Series - Verification of Next-Generation Mixed-Signal Communication SoC in 65/45nm Technologies
06/19/07Archived Webinar: Cadence Simulation & Verification Webinar Series - Verification of Complex Analog Designs
11/02/06Archived Webinar: Cadence Technology on Tour 2006 Demo Webinar Series: Virtuoso Multi-mode Simulation, complete solution for design and verification of analog, mixed-signal, RF, and custom digital designs
10/31/06Archived Webinar: Cadence Technology on Tour 2006 Demo Webinar Series: Leading-edge full-chip mixed-signal routing and DFM/DFY optimization
10/26/06Archived Webinar: Cadence Technology on Tour 2006 Demo Webinar Series: Introducing the Virtuoso Layout Suite
10/25/06Archived Webinar: Cadence Technology on Tour 2006 Demo Webinar Series: The new Virtuoso design environment
08/30/05Archived Webinar: RF IC design flow
08/25/05Archived Webinar: AMS block-level design flow
06/22/05Archived Webinar: Virtuoso Wireless Design Flows - RF IC and System/IC Designs
04/27/05Archived Webinar: Wireless Net Design Line Net Seminar - 802.11n vs. UWB: What's the Best Option?
08/31/04Archived Webinar: Technical Expert Webinar Series: Addressing Today's Custom Design Challenges (part 2 of 2): Layout Migration and Analog Design Automation
08/03/04Archived Webinar: Technical Expert Webinar Series—Addressing Today's Custom Design Challenges (part 1 of 2): What to do with Parasitics and Pragmatic Approaches to Designing Low-power Circuits
12/05/02Archived Webinar: Getting to 90nm and Beyond: Multisite Design Collaboration and Management Solutions in Cadence Custom IC Design