|
|
 |
 |
|
|
|
|
|
|
Home > Products > Virtuoso custom design > Products > Cadence Chip Optimizer
|
|
 |
Cadence Chip Optimizer
Cadence® Chip Optimizer is a silicon-proven, full-chip physical design optimization system that improves manufacturability, yield, and performance, thus addressing the ever-important requirements for shorter time to convergence and shorter time to volume. It optimizes layout based on electrical constraints, manufacturing rules, and objectives. Cadence Chip Optimizer is ideal for high-volume designs, designs at advanced process nodes, designs with critical time-to-volume requirements, and designs requiring minimal performance guard bands.
Cadence Chip Optimizer integrates with both the Encounter® digital IC and Virtuoso® custom IC design platforms.
Key benefits
 | Enables accurate, precise modeling and optimizations through a true hierarchical, three-dimensional space-based approach | | Provides faster, more reliable ramp-to-volume silicon with up to six points of yield improvement | | Ensures greater manufacturability and performance gains with powerful topological changes | | Handles complex and tiered rules and constraints at 65nm and below | | Improves design margins and reduces guard banding | | Eliminates convergence iterations through electrically (timing) correct design |
Visit the Cadence Designer Network User Community for user-contributed technical articles, product reviews, and interactive forums at www.cdnusers.org.
Read Encounter customer success stories and find out how others are succeeding with Encounter technology.
|
|
|
|
|
|
