High-capacity flat and hierarchical routing for complex custom ICsCadence Space-Based Router achieves shorter time to convergence and higher quality of silicon by simultaneously addressing multiple yield and manufacturability challenges
 Cadence Space-Based Router Datasheet » |
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 Growing design complexity and more digital and analog/mixed-signal content mean designers face critical yield and manufacturability challenges, such as lithography issues, inconsistent manufacturing rules, copper materials, electrical concerns, and performance requirements. Cadence® Space-Based Router addresses all these concerns simultaneously, helping designers achieve shorter time to convergence, better quality of silicon, and differentiated products for consumer and wireless markets.
Features/Benefits
- High capacity easily handles flat and hierarchical data for 250K net designs
- High-performance multi-threaded implementation accelerates completion of the largest designs
- Innovative hierarchical, 3-D, space-based architecture enables accurate modeling, manipulation, and checking of sophisticated geometries and constraints for sub-65nm interconnect design closure
- Signoff-quality advanced design-rule interconnect checking system delivers correct-by-construction design closure
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