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Custom IC Design
Circuit design
Selectively automating non-critical aspects of custom IC design allows engineers to focus on precision-crafting their designs. Cadence circuit design solutions enable fast and accurate entry of design concepts, which includes managing design intent in a way that flows naturally in the schematic. Using this advanced, parasitic-aware environment, you can abstract and visualize the many interdependencies of an analog, RF, or mixed-signal design to understand and determine their effects on circuit performance.
Virtuoso Schematic Editor
Provides a complete design and constraint composition environment for front-to-back analog, custom-digital, RF, and mixed-signal designs.
Learn more
»
Virtuoso Analog Design Environment
Provides a comprehensive array of capabilities for electrical and statistical analysis, verification, and optimization of analog/mixed-signal designs, including the interfaces to many industry-standard simulators.
Learn more
»
Virtuoso Visualization and Analysis
Cadence® Virtuoso® Visualization and Analysis is a waveform display and analysis tool that efficiently and thoroughly analyzes the performance of analog, RF, and mixed-signal designs.
Learn more
»
Block-level simulation
Cadence custom simulation technology delivers all the tools required for designing and verifying your analog/ mixed-signal blocks. Cadence offers multi-core, distributed SPICE simulation for realizing your design intent; higher capacity and performance with FastSPICE simulation using the same infrastructure and use model; and a mixed-signal simulation solution that leverages logic verification methodologies to improve your overall verification methodology. Cadence also delivers capabilities to abstract your design for architectural exploration and top-down verification methodology support.
Virtuoso Multi-Mode Simulation
Enables comprehensive design and verification by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle.
Learn more
»
Virtuoso Spectre Circuit Simulator
Delivers a fast, SPICE-accurate simulator for challenging analog, RF, and mixed-signal circuit simulation and device characterization.
Learn more
»
Virtuoso Accelerated Parallel Simulator
Delivers scalable performance and capacity at full Spectre-level accuracy across a broad range of complex analog, RF, and mixed-signal blocks and subsystems.
Learn more
»
Chip-level simulation
Leveraging custom design abstraction capabilities, Cadence chip-level simulation looks at all the blocks abstracted into a variety of languages combined with transistor-level blocks that converge on a whole design understanding. Cadence chip-level simulation solutions provide the large capacity and high performance required to ensure that a full chip is working as intended, regardless of how the blocks perform in aggregate.
Virtuoso Multi-Mode Simulation
Enables comprehensive design and verification by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle.
Learn more
»
Virtuoso Spectre Circuit Simulator
Delivers a fast, SPICE-accurate simulator for challenging analog, RF, and mixed-signal circuit simulation and device characterization.
Learn more
»
Virtuoso Accelerated Parallel Simulator
Delivers scalable performance and capacity at full Spectre-level accuracy across a broad range of complex analog, RF, and mixed-signal blocks and subsystems.
Learn more
»
Virtuoso UltraSim Full-Chip Simulator
Delivers the capacity, accuracy, and speed for transistor-level verification of large custom-analog, digital, mixed-signal, RF, memory, and SoC designs.
Learn more
»
Mixed-signal simulation
Today’s system-on-chip designs integrate complex analog and digital blocks, requiring thorough testing and analysis of how analog and digital circuits interact and the influence they have on each other. Cadence mixed-signal simulation solutions blend output results from industry-leading block-level and full-chip analog simulators with output from advanced digital analysis technologies. This superior approach to analysis also includes an extensive multi-language capability to support design abstraction and the ability to add in RF information.
Virtuoso Multi-Mode Simulation
Enables comprehensive design and verification by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle.
Learn more
»
Virtuoso AMS Designer
Provides an advanced mixed-signal simulation solution for design and verification of analog, RF, memory, and mixed-signal SoCs.
Learn more
»
Physical implementation
Physical implementation involves taking the design intent captured in the schematic and transforming it into a digital blueprint that represents how the chip will actually be manufactured. Cadence offers a correct-by-construction physical implementation solution that draws on design rules from the foundry as well as the custom designer’s own experience, enabling the software to perform place-and-route in a “custom” way.
Virtuoso Layout Suite
Provides the complete physical layout environment of the industry-standard Virtuoso custom design platform, a comprehensive solution for front-to-back custom-analog, digital, RF, and mixed-signal design.
Learn more
»
Virtuoso Digital Implementation
A complete and automatic synthesis/place-and-route system that enables capacity-limited block implementation for small digital components in the context of an advanced analog-driven mixed-signal design.
Learn more
»
Routing
Once all the devices in a design have been “placed down,” they must then be “connected up” with routing. Custom IC designers typically hand-route critical nets to limit the influence of parasitics. Cadence routing solutions take these hand-routing decisions and automate the routing of remaining nets based on design rules—which, at smaller nodes, are too numerous to reference manually.
Virtuoso Layout Suite
Provides the complete physical layout environment of the industry-standard Virtuoso custom design platform, a comprehensive solution for front-to-back custom-analog, digital, RF, and mixed-signal design.
Learn more
»
Virtuoso Chip Assembly Router
Performs automated and interactive block and chip authoring for custom-digital, mixed-signal, and analog designs—at any level of the hierarchy.
Learn more
»
Cadence Space-Based Router
Offers the performance and capacity to handle designs with growing complexity and increasing digital and analog/mixed-signal content.
Learn more
»
Parasitic extraction and analysis
After routing, designers must go back into the design to find the parasitics, and then perform another round of simulation to analyze where parasitic effects will conflict with the original design intent. Cadence solutions for parasitic extraction and analysis offer a holistic view of all the parasitic effects in a design, and then correct them as soon as possible by flagging violations of design rules in real time.
Virtuoso Power System
Enables custom design teams to efficiently analyze power and signal integrity for all designs implemented using a custom methodology.
Learn more
»
Virtuoso Analog Design Environment
Provides a comprehensive array of capabilities for electrical and statistical analysis, verification, and optimization of analog/mixed-signal designs, including the interfaces to many industry-standard simulators.
Learn more
»
Cadence QRC Extraction
The industry’s fastest, most accurate 3D full-chip parasitic extractor, delivering in-design and signoff extraction.
Learn more
»
Chip finishing
The final stage of creating a custom IC involves merging analog and digital elements by performing the top-most routing and power routing (power lines and clock trees). The Cadence approach to chip finishing integrates Encounter digital IC and Virtuoso custom IC design technologies in a seamless solution that implements full chips more efficiently and accurately.
Cadence Physical Verification System
The premier Cadence signoff solution enabling in-design and back-end physical verification, constraint validation, and reliability checking.
Learn more
»
Cadence Litho Physical Analyzer
Detects and corrects lithography hotspots. Uses a model-based technology to predict silicon contours quickly and accurately. Improves parametric yield and chip performance.
Learn more
»
Cadence Litho Electrical Analyzer
Extracts device and interconnect electrical behavior from contours. Detects and repairs timing and leakage hotspots due to systematic variations.
Learn more
»
Encounter Digital Implementation System
Delivers a complete solution for giga-gate/GHz, low-power, and mixed-signal designs at advanced and mainstream process nodes in a single, scalable multi-CPU–enabled design environment.
Learn more
»
Virtuoso Layout Suite
Provides the complete physical layout environment of the industry-standard Virtuoso custom design platform, a comprehensive solution for front-to-back custom-analog, digital, RF, and mixed-signal design.
Learn more
»
Manufacturability signoff
At today’s advanced process nodes, custom IC design software must account for challenges of smaller transistors and wires, as well as the data capacity and complexity of denser and more complex chips. Cadence solutions for manufacturability take the knowledge of creating the mask and how the chip is going to be manufactured and bring it back into the design phase. This helps designers compensate for physical effects at nanometer geometries while providing a reliable way to achieve manufacturing signoff before tapeout.
Assura Physical Verification
Performs design-rule checking and layout vs. schematic verification to deliver high-yielding custom IP for SoC designs.
Learn more
»
Cadence Physical Verification System
The premier Cadence signoff solution enabling in-design and back-end physical verification, constraint validation, and reliability checking.
Learn more
»
Cadence Chip Optimizer
Uses a 3D space-based approach that models, analyzes, and optimizes layout according to electrical constraints, manufacturing rules, and objectives.
Learn more
»
Cadence Litho Physical Analyzer
Detects and corrects lithography hotspots. Uses a model-based technology to predict silicon contours quickly and accurately. Improves parametric yield and chip performance.
Learn more
»
Cadence Litho Electrical Analyzer
Extracts device and interconnect electrical behavior from contours. Detects and repairs timing and leakage hotspots due to systematic variations.
Learn more
»
Virtuoso DFM
Accurately assess both physical and electrical variability to ensure the manufacturability of custom and mixed-signal designs, libraries, and IP.
Learn more
»
Cadence CMP Predictor
Optimizes design performance through model-based intelligent metal fill and hotspot detection and correction.
Learn more
»
Virtuoso Foundation IP Characterization
Virtuoso Foundation IP Characterization delivers the industry’s most complete and robust solutions for the characterization and validation of your foundation IP from standard cells, standard I/O’s, complex I/O’s and memories. Patented “Inside-view” technology delivers faster time to market, better correlation to silicon by improving library throughput and ensuring timing, power, noise and statistical coverage of your cells.
Virtuoso Liberate
Provides an ultra-fast cell library characterization solution for standard cells and complex I/Os supporting advanced timing, power and signal integrity DC current source models (CCS, ECSM).
Learn more
»
Virtuoso Liberate MX
Enables fast and accurate characterization of large embedded memories to create instance specific memory models for timing, power and noise.
Learn more
»
Virtuoso Liberate LV
Provides a comprehensive library validation system including function equivalence and data consistency checking, revision analysis and correlation with various electrical analysis tools for timing, noise and power.
Learn more
»
Virtuoso Variety
Enables fast, accurate general purpose process variation characterization to generate library models for Statistical Static Timing Analysis (SSTA).
Learn more
»
Library development
Developing libraries of cells matched to a particular manufacturing process is critical at smaller geometries. Cadence library development solutions not only automate cell development, library validation, and creation of component technologies, but also facilitate IP reuse.
Virtuoso Layout Migrate
Offers rapid physical layout migration, including support for complex design rules at advanced nodes.
Learn more
»
Assura Physical Verification
Performs design-rule checking and layout vs. schematic verification to deliver high-yielding custom IP for SoC designs.
Learn more
»
Cadence Chip Optimizer
Uses a 3D space-based approach that models, analyzes, and optimizes layout according to electrical constraints, manufacturing rules, and objectives.
Learn more
»
Cadence CMP Predictor
Optimizes design performance through model-based intelligent metal fill and hotspot detection and correction.
Learn more
»
Cadence Litho Electrical Analyzer
Extracts device and interconnect electrical behavior from contours. Detects and repairs timing and leakage hotspots due to systematic variations.
Learn more
»
Cadence Litho Physical Analyzer
Detects and corrects lithography hotspots. Uses a model-based technology to predict silicon contours quickly and accurately. Improves parametric yield and chip performance.
Learn more
»
Cadence Physical Verification System
The premier Cadence signoff solution enabling in-design and back-end physical verification, constraint validation, and reliability checking.
Learn more
»
Cadence QRC Extraction
The industry’s fastest, most accurate 3D full-chip parasitic extractor, delivering in-design and signoff extraction.
Learn more
»
Cadence Space-Based Router
Offers the performance and capacity to handle designs with growing complexity and increasing digital and analog/mixed-signal content.
Learn more
»
Encounter Digital Implementation System
Delivers a complete solution for giga-gate/GHz, low-power, and mixed-signal designs at advanced and mainstream process nodes in a single, scalable multi-CPU–enabled design environment.
Learn more
»
Virtuoso Accelerated Parallel Simulator
Delivers scalable performance and capacity at full Spectre-level accuracy across a broad range of complex analog, RF, and mixed-signal blocks and subsystems.
Learn more
»
Virtuoso AMS Designer
Provides an advanced mixed-signal simulation solution for design and verification of analog, RF, memory, and mixed-signal SoCs.
Learn more
»
Virtuoso Analog Design Environment
Provides a comprehensive array of capabilities for electrical and statistical analysis, verification, and optimization of analog/mixed-signal designs, including the interfaces to many industry-standard simulators.
Learn more
»
Virtuoso Chip Assembly Router
Performs automated and interactive block and chip authoring for custom-digital, mixed-signal, and analog designs—at any level of the hierarchy.
Learn more
»
Virtuoso DFM
Accurately assess both physical and electrical variability to ensure the manufacturability of custom and mixed-signal designs, libraries, and IP.
Learn more
»
Virtuoso Digital Implementation
A complete and automatic synthesis/place-and-route system that enables capacity-limited block implementation for small digital components in the context of an advanced analog-driven mixed-signal design.
Learn more
»
Virtuoso Layout Migrate
Offers rapid physical layout migration, including support for complex design rules at advanced nodes.
Learn more
»
Virtuoso Layout Suite
Provides the complete physical layout environment of the industry-standard Virtuoso custom design platform, a comprehensive solution for front-to-back custom-analog, digital, RF, and mixed-signal design.
Learn more
»
Virtuoso Liberate
Provides an ultra-fast cell library characterization solution for standard cells and complex I/Os supporting advanced timing, power and signal integrity DC current source models (CCS, ECSM).
Learn more
»
Virtuoso Liberate LV
Provides a comprehensive library validation system including function equivalence and data consistency checking, revision analysis and correlation with various electrical analysis tools for timing, noise and power.
Learn more
»
Virtuoso Liberate MX
Enables fast and accurate characterization of large embedded memories to create instance specific memory models for timing, power and noise.
Learn more
»
Virtuoso Multi-Mode Simulation
Enables comprehensive design and verification by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle.
Learn more
»
Virtuoso Power System
Enables custom design teams to efficiently analyze power and signal integrity for all designs implemented using a custom methodology.
Learn more
»
Virtuoso Schematic Editor
Provides a complete design and constraint composition environment for front-to-back analog, custom-digital, RF, and mixed-signal designs.
Learn more
»
Virtuoso Spectre Circuit Simulator
Delivers a fast, SPICE-accurate simulator for challenging analog, RF, and mixed-signal circuit simulation and device characterization.
Learn more
»
Virtuoso UltraSim Full-Chip Simulator
Delivers the capacity, accuracy, and speed for transistor-level verification of large custom-analog, digital, mixed-signal, RF, memory, and SoC designs.
Learn more
»
Virtuoso Variety
Enables fast, accurate general purpose process variation characterization to generate library models for Statistical Static Timing Analysis (SSTA).
Learn more
»
Virtuoso Visualization and Analysis
Cadence® Virtuoso® Visualization and Analysis is a waveform display and analysis tool that efficiently and thoroughly analyzes the performance of analog, RF, and mixed-signal designs.
Learn more
»
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