Analog Devices Anthony Agrillo Analog Devices Anthony Agrillo, a layout engineer at Analog Devices, works with a team that needs to build small-scale, non-timing digital blocks to go with the analog blocks in their design. Frustrated at how long their manual process took, the team turned to the Cadence® Virtuoso® Custom Placer and Virtuoso Space-based Router in Cadence's Virtuoso Layout Suite. Watch the video to find out how much time the team is saving and how much more efficient their process is.
Allegro Microsystems Steve Nedeau Allegro Microsystems Allegro Microsystems has small, custom digital blocks to implement. By hand, such designs were taking up to three days to complete. With the Virtuoso® Custom Placer and Virtuoso Space-based Router in Cadence's Virtuoso Layout Suite, Allegro cut that place-and-route time down to a less than a day and reduced its block size by 30%. Watch the video to hear what Steve Nedeau, senior IC layout engineer, says about how the tools have made his life easier.
ams Thomas Moerth ams Engineers at ams AG were frustrated at how long it was taking to verify their mixed-signal designs. If there wasn't enough time in the schedule, the trade-off was to not verify everything, but risk having chips that didn't work as expected. Knowing that they had reached their limits with the hardware, the ams team turned to software for an answer. In this short video, Thomas Moerth, the company's manager of Design Support, Full-Service Foundry, talks about how Cadence® Virtuoso® AMS Designer helped ams complete 2X the number of simulations as was previously possible and how Cadence Spectre® Extensive Partitioning Simulator helped boost simulation speed by 10X.
Analog Devices Eduard Raines Analog Devices Watch this video to learn how Analog Devices ramped up engineering productivity using ModGen tools in Cadence's Virtuoso® Layout Suite solution. CAD engineer Eduard Raines explains how his team replaced time-consuming manual processes with an automated solution to create custom programs for high performance, highly matched design structures.
Bosch Peter van Staa
Peter van Staa, Vice President of Engineering at Bosch highlights how they improved design efficiency by 25% utilizing the Cadence Design Environment.
Chris Silsby Agilent Technologies Chris Silsby from Agilent Technologies talks about how the Virtuoso accelerated layout technologies help Agilent complete a variety of experiments in hours instead of weeks, and complete the project on schedule.
austriamicrosystems Thomas Riener austriamicrosystems
Thomas Riener, Sr. VP, General Manager Foundry Business at austriamicrosystems describes how they leverage the Cadence unified custom/analog flow to design the company’s analog IC products.
austriamicrosystems Douglas Pattullo austriamicrosystems Douglas Pattullo talks about how the robust and stable technologies from the Virtuoso custom design platform help austriamicrosystems build design kits that facilitate fast, productive design to market.
Digeo Toby Farrand Digeo Toby Farrand, Chief Technical Officer of Digeo talks about how Digeo and Cadence Engineerings Services collaborate to achieve first silicon success on X-Stream project.
Intrinsity Tom Rudwick Intrinsity Tom Rudwick of Intrinsity talks about how the Virtuoso accelerated layout technologies, with its easy-to-use shape-based router, help Intrinsity to meet electromigration constraints and design to volume.
Melexis Business Challenge
Accelerate design process
Increase design productivity
Lower design costs Design Challenges
Streamline design and verification process
Find and fix bugs faster
Achieve higher level of design abstraction Cadence Solutions
Cadence Incisive Enterprise Simulator
Cadence Incisive Software Extensions
Cadence SimVision Debug
Cadence Virtuoso Analog Design Environment Results
15% reduction in IC development time
200X faster simulation via transaction-level model
Earlier detection/resolution of bugs
Enhanced collaboration between analog and software teams Read full story »
Rohde & Schwarz
Steve Stern Sipex Steve Stern from Sipex talks about how the Virtuoso custom design platform and Cadence Engineering Services provided technologies and methodologies that reduced design cycle time from months to weeks and increased employee retention.
Texas Instruments Business Challenge
Fast time to market and stringent quality and budget goals for SoC designs and foundation IP Design Challenges
Speed turnaround time for simulation and characterization of compiler memories
Achieve desired level of results accuracy Cadence Solutions
Virtuoso Foundation IP Characterization
Virtuoso Liberate MX
Spectre APS Results
Achieved full SRAM simulation for today’s SoC timing and leakage and static power requirements
Achieved a 2X reduction in characterization cycle time compared to previous solution
Met quality-of-results goals Read full story »
Virage Logic Ken Rousseau Virage Logic Ken Rousseau, VP Software Development of Virage Logic talks about how Virage Logic delivers memory compiler using high-performance, industry-standard Virtuoso custom IC layout.
Edwin Li Zeevo Edwin Li, Ph.D. from Zeevo talks about how the Virtuoso custom design platforms speeds the design of highly integrated Bluetooth SoC RF modules by enabling simulation of designs at real-time 2.4-gigahertz speed through the Virtuoso AMS Designer Simulator.
Global Unichip Albert Li Global Unichip Watch this video for insights into Global Unichip's successful tapeout of a 20nm testchip with Cadence and TSMC. Albert Li, marketing director at Global Unichip, talks about the collaborative effort and overcoming advanced node challenges such as double patterning and new design rules.
IBM Sangtae Bae IBM Transistor-Level Reliability Analysis for Advanced Node Description: Sangtae Bae, an analog/mixed-signal circuit designer at IBM, designs high-speed interfaces for IBM's server chips. Bae and his team needed a method to verify circuits will operate in silicon, reliably well over expected life of products. In this 4-minute video, Bae explains how reliability simulation in Cadence® Spectre® Accelerated Parallel Simulator (APS) ran from Cadence Virtuoso® Analog Design Environment (ADE) helped IBM perform reliability analysis efficiently and get to market faster with its server chips.
Micron Technology David Paquet & Julie Sulisthio Sr. CAD Manager & Sr. CAD Engineer at Micron Technology Hear from David Paquet, Sr. CAD Manager and Julie Sulisthio, Sr. CAD Engineer from Micron Technology as they talk about the use of Physical Verification System Constraint Validator in conjunction with Virtuoso Constraint System to validate design intent and improve design quality.
PMC Vivekanand Malkane PMC Engineers at PMC were frustrated with their slow, manual process for verifying analog IP and developing functional models. To automate its processes, the company implemented Cadence® Virtuoso® Schematic Editor and a SystemVerilog testbench. In this video, Vivekanand Malkane, technical manager of the mixed-signal verification team at PMC, talks about how much more efficient the team's verification process is.
S3 S3 Flavio Cali Hear from Flavio Cali with S3 Group, as he highlights the user experience of Cadence Physical Verification System (PVS) for SoC design.
STMicroelectronics Romain Feuillette
STMicroelectronics Romain Feuillette, Team Leader at STMicroelectronics, talks about succeeding with the Cadence innovative Virtuoso custom/analog flow to meet aggressive roadmaps and improve productivity at all process nodes.
STMicroelectronics Vincent Varo STMicroelectronics Vincent Varo, Design Kit & Support Manager, at STMicroelectronics discusses the use of Virtuoso Integrated Physical Verification System to address the challenges of 20nm designs.
STMicroelectronics Romain Feuillette
STMicroelectronics Romain Feuillette, Team Leader at STMicroelectronics describes the benefits of using the Cadence Virtuoso-based custom/analog flow to enable faster time to market, higher productivity, and product innovation.
STMicroelectronics Preeti Kapoor STMicroelectronics At advanced process nodes, new challenges such as layout-dependent effects emerge. STMicroelectronics needed to address these challenges and automate its full custom analog layout flow. Watch this video to hear Preeti Kapoor, a design engineer at the company, talk about using design constraints (specifically, modgens) to create a faster and more accurate DRC clean design.
STMicroelectronics Livio Frantantonio STMicroelectronics STMicroelectronics relies on mixed-signal solutions for its Smart Power Technologies. As Livio Frantantonio explains in this video, STMicro needed to increase productivity and quality of results while shortening its turnaround times. The company found its answer in Cadence's mixed-signal solutions, including Virtuoso® Mixed-Signal Flow. Watch this video to learn how STMicro benefited from using the Cadence Unified Mixed-Signal Methodology.
Touchstone Semiconductor Dr. Jeroen Fonderie Touchstone Semiconductor Taping out 17 different projects over 3 1/2 years seemed like a tall order for Touchstone Semiconductor. But with a helping hand from Cadence Hosted Design Solutions, the startup got its CAD environment set up smoothly and has successfully rolled out 71 high-performance analog ICs since its founding in 2010. Simply put, Hosted Design Solutions lets Touchstone focus on what it does best - designing circuits. Watch this video to hear the company’s VP of engineering, Dr. Jeroen Fonderie, discuss how Cadence helped his company get off the ground.
Triune Systems Ross Teggatz Triune Systems Ross Teggatz, President/Founder at Triune Systems outlines the values of using the Cadence unified digital and unified custom/analog flows to meet their mixed-signal design requirements and close time to market gaps.
TSMC Maria Marced TSMC Europe Maria Marced, President of TSMC Europe, discusses with Christian Malter, Director Technology Solutions, EMEA, Cadence, the significance of 16nm FinFET technology and highlights their collaboration with Cadence.
TSMC Maria Marced TSMC Europe Maria Marced, President of TSMC Europe, and Christian Malter, Director Technology Solutions, EMEA, Cadence, discuss how customers benefit from the collaboration between the two companies in the mixed-signal space.