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Cadence Chip Optimizer 


Manufacturing-aware full-chip modeling and layout optimization

Cadence Chip Optimizer uses an innovative space-based approach to address the most demanding sub-wavelength lithography and manufacturing process rules.

Cadence Chip Optimizer Datasheet »

Conventional IC implementation tools create oversimplified models of interconnect. Cadence® Chip Optimizer is a silicon-proven, full-chip physical design optimization system that improves manufacturability, yield, and performance. It optimizes layout based on electrical constraints, manufacturing rules, and timing objectives.

Cadence Chip Optimizer is ideal for designing with advanced process nodes, critical time-to-volume requirements, and minimal performance guardbands. Cadence Chip Optimizer uses a true hierarchical 3D space-based approach that models, analyzes, and optimizes true shapes and intervening physical spaces. It allows shapes and spaces to be positioned in the exact configuration and location required to correct sub-wavelength spacing and topological effects. This capability affords greater precision and flexibility when optimizing interconnect while using tiered design and manufacturing constraints.

Features/Benefits
  • Enables accurate interconnect modeling and layout optimization through an innovative space-based approach
  • Ensures greater manufacturability and performance gains with powerful topological changes
  • Handles complex and tiered rules and constraints at 65nm and below
  • Improves design margins and reduces guardbanding
  • Eliminates convergence iterations through electrically (timing)-correct design
  • Integrates with both Encounter® digital and Virtuoso® custom design technologies