Cadence.com will be under system maintenance from Tuesday June 28, 6pm PT to Sunday July 3, 11pm PT. Login and registration will be disabled.
Home > Tools > Custom IC Design > Cadence Chip Optimizer > Resource Library

Cadence Chip Optimizer 


Manufacturing-aware full-chip modeling and layout optimization

Cadence Chip Optimizer uses an innovative space-based approach to address the most demanding sub-wavelength lithography and manufacturing process rules.

Cadence Chip Optimizer Datasheet »
4 resources found
 
Title Type Rated
Using Cadence Chip Optimizer with SoC Encounter GXL for Design Closure
Format: .PDF (1MB)    Date: 15 Sep 2007
Conference Paper
 0
Recommend!
Performance Impact from Metal Fill Insertion
Format: .PDF    Date: 15 Sep 2007
Conference Paper
 1
Recommend!
Cadence Space-Based Router, the next generation
Format: .PDF    Date: 17 Apr 2007
Cadence Article
 0
Recommend!
Cadence Chip Optimizer Datasheet
Format: .PDF (1.3MB)    Date: 01 Apr 2006
Datasheet
 0
Recommend!