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Press Releases
Cadence Announces Virtuoso Liberate AMS, Industry’s First Dynamic Simulation Characterization Solution for Mixed-Signal Designs
TSMC Adopts Cadence Solutions for 16nm FinFET Library Characterization
Cadence Significantly Accelerates Chip Design With New Virtuoso for Electrically Aware Design

Electrically-aware design improves analog/mixed-signal productivity
Taming The Challenges Of 20nm Custom/Analog Design
TSMC Validates Cadence 3D-IC Technology for Its CoWoS(TM) Reference Flow

Autonomous Car Silicon Valley 2016
02/24/2016 - San Francisco
CDNLive Silicon Valley
04/05/2016 - Santa Clara Convention Center
05/02/2016 - Dolce Hotel Unterschleissheim

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