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Press Releases
Cadence Announces Virtuoso Liberate AMS, Industry’s First Dynamic Simulation Characterization Solution for Mixed-Signal Designs
TSMC Adopts Cadence Solutions for 16nm FinFET Library Characterization
Cadence Significantly Accelerates Chip Design With New Virtuoso for Electrically Aware Design

Electrically-aware design improves analog/mixed-signal productivity
Taming The Challenges Of 20nm Custom/Analog Design
TSMC Validates Cadence 3D-IC Technology for Its CoWoS(TM) Reference Flow

TSMC 2015 Technical Symposium
04/07/2015 - 7 Apr — San Jose McEnery Convention Center, San Jose, CA; 14 Apr — Marriott Burlington, MA; 16 Apr — Hilton (Downtown), Austin, TX
CDNLive EMEA 2015
04/27/2015 - Munich
CDNLive Korea
07/15/2015 - Seoul

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