Anthony Agrillo, a layout engineer at Analog Devices, works with a team that needs to build small-scale, non-timing digital blocks to go with the analog blocks in their design. Frustrated at how long their manual process took, the team turned to the Cadence® Virtuoso® Custom Placer and Virtuoso Space-based Router in Cadence's Virtuoso Layout Suite. Watch the video to find out how much time the team is saving and how much more efficient their process is.
Allegro Microsystems has small, custom digital blocks to implement. By hand, such designs were taking up to three days to complete. With the Virtuoso® Custom Placer and Virtuoso Space-based Router in Cadence's Virtuoso Layout Suite, Allegro cut that place-and-route time down to a less than a day and reduced its block size by 30%. Watch the video to hear what Steve Nedeau, senior IC layout engineer, says about how the tools have made his life easier.
Engineers at ams AG were frustrated at how long it was taking to verify their mixed-signal designs. If there wasn't enough time in the schedule, the trade-off was to not verify everything, but risk having chips that didn't work as expected. Knowing that they had reached their limits with the hardware, the ams team turned to software for an answer. In this short video, Thomas Moerth, the company's manager of Design Support, Full-Service Foundry, talks about how Cadence® Virtuoso® AMS Designer helped ams complete 2X the number of simulations as was previously possible and how Cadence Spectre® Extensive Partitioning Simulator helped boost simulation speed by 10X.
At ams AG, the engineering team had been performing electromigration checks at signoff. As a result, problems were detected late in the cycle, so the team had to make additional efforts to fix these problems. This was a costly approach that could potentially delay the project. Watch this short Expert Insights video to hear Bertram Winter, a design support engineer at ams, explain how Cadence's electrically aware design flow helped the team revamp its process to avoid additional design iterations.
Watch this video to learn how Analog Devices ramped up engineering productivity using ModGen tools in Cadence's Virtuoso® Layout Suite solution. CAD engineer Eduard Raines explains how his team replaced time-consuming manual processes with an automated solution to create custom programs for high performance, highly matched design structures.
Peter van Staa
Peter van Staa, Vice President of Engineering at Bosch highlights how they improved design efficiency by 25% utilizing the Cadence Design Environment.
- High levels of signal processing and careful design to minimize power consumption and maximize performance for advanced LTE technologies
- High costs related to IP licensing of different SoC components, tapeouts in advanced process geometries, carrier certifications and software investments
- Aggressive time to market and price targets for chipsets
- Complete suite of analog IP
- Analog design and integration expertise
- Controller and PHY IP for LPDDR2, USB 2.0 ,and M-PCIe™ interfaces
- Designing with Cadence silicon-proven analog IP is the best solution to reduce cost, accelerate time to market
- Always work upfront with the IP vendor on AFE definition
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- Ability to compete in the rapidly growing LTE market space
- Up to eight months faster time to market
- Leading-edge products at a lower cost in terms of time, engineering, and tapeout
Chris Silsby from Agilent Technologies talks about how the Virtuoso accelerated layout technologies help Agilent complete a variety of experiments in hours instead of weeks, and complete the project on schedule.
Thomas Riener, Sr. VP, General Manager Foundry Business at austriamicrosystems describes how they leverage the Cadence unified custom/analog flow to design the company’s analog IC products.
Douglas Pattullo talks about how the robust and stable technologies from the Virtuoso custom design platform help austriamicrosystems build design kits that facilitate fast, productive design to market.
Toby Farrand, Chief Technical Officer of Digeo talks about how Digeo and Cadence Engineerings Services collaborate to achieve first silicon success on X-Stream project.
- Improve efficiency of top-level verification of mixed-signal SoCs
- Tap into expertise of digital and analog engineers for top-level verification
- Virtuoso Analog Design Environment
- Virtuoso AMS Designer Simulator
- SimVision Debug
- Incisive vManager solution
- To ensure backwards compatibility to the legacy directed-test environment, use compiler directives to constrain random stimulus
- When using a coverage- or metric-driven approach, simulation throughput is crucial, so it’s important to collect enough metrics
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- Orders-of-magnitude faster top-level verification of mixed-signal SoCs using wreal configurations
- 2X more verification productivity for digital and analog engineers achieved through rapid simulation launch and re-invoke
- Better coverage and traceability with Incisive vManager solution
- Better bug detection using behavior wreal models verified against actual schematics
Tom Rudwick of Intrinsity talks about how the Virtuoso accelerated layout technologies, with its easy-to-use shape-based router, help Intrinsity to meet electromigration constraints and design to volume.
- Accelerate design process
- Increase design productivity
- Lower design costs
- Streamline design and verification process
- Find and fix bugs faster
- Achieve higher level of design abstraction
- Cadence Incisive Enterprise Simulator
- Cadence Incisive Software Extensions
- Cadence SimVision Debug
- Cadence Virtuoso Analog Design Environment
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- 15% reduction in IC development time
- 200X faster simulation via transaction-level model
- Earlier detection/resolution of bugs
- Enhanced collaboration between analog and software teams
Rohde & Schwarz
Steve Stern from Sipex talks about how the Virtuoso custom design platform and Cadence Engineering Services provided technologies and methodologies that reduced design cycle time from months to weeks and increased employee retention.
- Fast time to market and stringent quality and budget goals for SoC designs and foundation IP
- Speed turnaround time for simulation and characterization of compiler memories
- Achieve desired level of results accuracy
- Virtuoso Foundation IP Characterization
- Virtuoso Liberate MX
- Spectre XPS
- Spectre APS
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- Achieved full SRAM simulation for today’s SoC timing and leakage and static power requirements
- Achieved a 2X reduction in characterization cycle time compared to previous solution
- Met quality-of-results goals
Ken Rousseau, VP Software Development of Virage Logic talks about how Virage Logic delivers memory compiler using high-performance, industry-standard Virtuoso custom IC layout.
Edwin Li, Ph.D. from Zeevo talks about how the Virtuoso custom design platforms speeds the design of highly integrated Bluetooth SoC RF modules by enabling simulation of designs at real-time 2.4-gigahertz speed through the Virtuoso AMS Designer Simulator.
Watch this 1 1/2-minute video to hear how Chris Bennett, ASIC layout engineer at Fairchild Semiconductor, solved a floorplanning challenge in a mixed-signal design using Cadence® Virtuoso® custom design and Cadence® Digital Implementation platforms. Routing power to hard macros inside the digital portion of the design was difficult, until the team began using the combined Cadence mixed-signal implementation solution, which also helped assure them that they would meet their EMIR requirements.
Freescale introduced constraint-driven design into its environment in 2014 and in that year, completed more than 700 runs using customized constraint bundles developed with SKILL API. Julia Perez, a PDK/CAD developer at the company, is responsible for automation and adoption of constraint-driven design for analog technologies. Watch this video to hear Perez talk about lessons learned and successes achieved with constraint-driven design using Cadence® Virtuoso® Schematic Editor XL and Cadence Virtuoso Layout Suite XL.
Watch this video for insights into Global Unichip's successful tapeout of a 20nm testchip with Cadence and TSMC. Albert Li, marketing director at Global Unichip, talks about the collaborative effort and overcoming advanced node challenges such as double patterning and new design rules.
Transistor-Level Reliability Analysis for Advanced Node Description: Sangtae Bae, an analog/mixed-signal circuit designer at IBM, designs high-speed interfaces for IBM's server chips. Bae and his team needed a method to verify circuits will operate in silicon, reliably well over expected life of products. In this 4-minute video, Bae explains how reliability simulation in Cadence® Spectre® Accelerated Parallel Simulator (APS) ran from Cadence Virtuoso® Analog Design Environment (ADE) helped IBM perform reliability analysis efficiently and get to market faster with its server chips.
David Paquet & Julie Sulisthio
Sr. CAD Manager & Sr. CAD Engineer at Micron Technology
Hear from David Paquet, Sr. CAD Manager and Julie Sulisthio, Sr. CAD Engineer from Micron Technology as they talk about the use of Physical Verification System Constraint Validator in conjunction with Virtuoso Constraint System to validate design intent and improve design quality.
Engineers at PMC were frustrated with their slow, manual process for verifying analog IP and developing functional models. To automate its processes, the company implemented Cadence® Virtuoso® Schematic Editor and a SystemVerilog testbench. In this video, Vivekanand Malkane, technical manager of the mixed-signal verification team at PMC, talks about how much more efficient the team's verification process is.
Watch this 2-minute video to hear Vinayak Bhat, a staff mixed-signal verification engineer at PMC-Sierra, explain how he and his team improved timing characterization of analog macros using Cadence® Virtuoso® Liberate™ AMS Mixed-Signal Characterization Solution. With a timing path buried deep in the hierarchy and too many manual interventions, the team revamped its processes using the Virtuoso tool.
Hear from Flavio Cali with S3 Group, as he highlights the user experience of Cadence Physical Verification System (PVS) for SoC design.
Romain Feuillette, Team Leader at STMicroelectronics, talks about succeeding with the Cadence innovative Virtuoso custom/analog flow to meet aggressive roadmaps and improve productivity at all process nodes.
Vincent Varo, Design Kit & Support Manager, at STMicroelectronics discusses the use of Virtuoso Integrated Physical Verification System to address the challenges of 20nm designs.
Romain Feuillette, Team Leader at STMicroelectronics describes the benefits of using the Cadence Virtuoso-based custom/analog flow to enable faster time to market, higher productivity, and product innovation.
At advanced process nodes, new challenges such as layout-dependent effects emerge. STMicroelectronics needed to address these challenges and automate its full custom analog layout flow. Watch this video to hear Preeti Kapoor, a design engineer at the company, talk about using design constraints (specifically, modgens) to create a faster and more accurate DRC clean design.
STMicroelectronics relies on mixed-signal solutions for its Smart Power Technologies. As Livio Frantantonio explains in this video, STMicro needed to increase productivity and quality of results while shortening its turnaround times. The company found its answer in Cadence's mixed-signal solutions, including Virtuoso® Mixed-Signal Flow. Watch this video to learn how STMicro benefited from using the Cadence Unified Mixed-Signal Methodology.
Dr. Jeroen Fonderie
Taping out 17 different projects over 3 1/2 years seemed like a tall order for Touchstone Semiconductor. But with a helping hand from Cadence Hosted Design Solutions, the startup got its CAD environment set up smoothly and has successfully rolled out 71 high-performance analog ICs since its founding in 2010. Simply put, Hosted Design Solutions lets Touchstone focus on what it does best - designing circuits. Watch this video to hear the company’s VP of engineering, Dr. Jeroen Fonderie, discuss how Cadence helped his company get off the ground.
Ross Teggatz, President/Founder at Triune Systems outlines the values of using the Cadence unified digital and unified custom/analog flows to meet their mixed-signal design requirements and close time to market gaps.
Maria Marced, President of TSMC Europe, discusses with Christian Malter, Director Technology Solutions, EMEA, Cadence, the significance of 16nm FinFET technology and highlights their collaboration with Cadence.
Maria Marced, President of TSMC Europe, and Christian Malter, Director Technology Solutions, EMEA, Cadence, discuss how customers benefit from the collaboration between the two companies in the mixed-signal space.