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Products A - Z
Cadence delivers application specific kits and new-generation platforms of integrated design technologies and methodologies that help you address all aspects of electronics design in the nanometer era.
3
3D Design Viewer
A
Allegro AMS Simulator
Allegro Design Entry CIS
Allegro Design Entry HDL
Allegro Design Publisher
Allegro Design Workbench
Allegro FPGA System Planner
Allegro Package Designer
Allegro Package SI
Allegro PCB Design
Allegro PCB Librarian XL
Allegro PCB SI
Allegro System Architect
AMS Methodology Kit
Assura Physical Verification
C
Cadence 3D Design Viewer
Cadence ActiveParts Portal
Cadence AMS Methodology Kit
Cadence Chip Optimizer
Cadence Chip Planning System
Cadence CMP Predictor
Cadence InCyte Chip Estimator
Cadence Litho Electrical Analyzer
Cadence Litho Physical Analyzer
Cadence Low-Power Methodology Kit
Cadence MaskCompose Reticle and Wafer Synthesis Suite
Cadence OrCAD Capture / Capture CIS
Cadence OrCAD FPGA System Planner
Cadence OrCAD PCB Designer
Cadence OrCAD Signal Explorer
Cadence Physical Verification System
Cadence PSpice A/D and Advanced Analysis
Cadence QRC Extraction
Cadence QuickView Layout and Manufacturing Data Viewer
Cadence RF Design Methodology Kit
Cadence RF SiP Methodology Kit
Cadence SiP Digital Architect
Cadence SiP Digital Layout
Cadence SiP Digital SI
Cadence SiP RF Architect
Cadence SiP RF Layout
Cadence SOC Functional Verification Kit
Cadence Space-Based Router
Cadence SpeedBridge Adapters
Chip Optimizer
Chip Planning System
CMP Predictor
C-to-Silicon Compiler
E
Encounter Conformal Constraint Designer
Encounter Conformal ECO Designer
Encounter Conformal Equivalence Checker
Encounter Conformal Low Power
Encounter DFT Architect
Encounter Diagnostics
Encounter Digital Implementation System
Encounter Library Characterizer
Encounter Power System
Encounter RTL Compiler
Encounter RTL Compiler with Physical
Encounter Timing System
Encounter True-Time ATPG
F
First Encounter Silicon Virtual Prototyping
I
Incisive Design Team Simulator
Incisive Desktop Manager
Incisive Enterprise Manager
Incisive Enterprise Simulator
Incisive Enterprise Specman Elite Testbench
Incisive Enterprise Verifier
Incisive Formal Verifier
Incisive Palladium Dynamic Power Analysis
Incisive Palladium series
Incisive Plan-to-Closure Methodology
Incisive Software Extensions
Incisive Verification IP
Incisive Xtreme series
InCyte Chip Estimator
L
Litho Electrical Analyzer
Litho Physical Analyzer
Low-Power Methodology Kit
M
MaskCompose Reticle and Wafer Synthesis Suite
N
NanoRoute Router
O
Open Verification Methodology
OrCAD Capture and Capture CIS
OrCAD PCB Designer
OrCAD Signal Explorer
P
Physical Verification System
PSpice A/D and Advanced Analysis
Q
QRC Extraction
QuickView Layout and Manufacturing Data Viewer
R
RF Design Methodology Kit
RF SiP Methodology Kit
S
SiP Digital Architect
SiP Digital Layout
SiP Digital SI
SiP RF Architect
SiP RF Layout
SoC Encounter RTL-to-GDSII System
SoC Functional Verification Kit
Space-Based Router
SpeedBridge Adapters
V
Virtuoso Accelerated Parallel Simulator
Virtuoso AMS Designer
Virtuoso Analog Design Environment
Virtuoso Chip Assembly Router
Virtuoso Digital Implementation
Virtuoso Layout Migrate
Virtuoso Layout Suite
Virtuoso Multi-Mode Simulation
Virtuoso Schematic Editor
Virtuoso Spectre Circuit Simulator
Virtuoso UltraSim Full-Chip Simulator
VoltageStorm Power Verification
Content Query Web Part [1]
White paper: Eliminating Routing Congestion Issues with Logic Synthesis
Archived webinar - Understanding Impact of Implementation Choices, Linking Back to Original IC Design Goals
Content Editor Web Part [3]
Design Communities
System Design and Verification
Functional Verification
Logic Design
Digital Implemntation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Sign-off
Design Community Home
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Content Query Web Part [2]
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