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Technical Info

This page contains technical information related to Standards and Languages, including application notes, white papers, and articles.

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White papers



AMSUltra: Virtuoso AMS Simulator With Virtuoso UltraSim FastSPICE Solver Download PDF
TFT Design Verification With Virtuoso UltraSim Full-chip Simulator Download PDF
Design for Test Methodology—Case Study for Motorola C-5e DCP Using the Cadence Incisive Accelerator/Emulator Download PDF
The Role of Design in Enhancing Nanometer Process Yield Download PDF
Transaction-based co-simulation with Verisity Specman Elite Download PDF
more white papers

Articles



02/14/05IEEE SystemVerilog Heads Towards Balloting
11/29/04SystemC Presses IEEE Standardization
11/19/04Focus On Results in System Language Debate
10/11/04Methodology Sought For Assertion-based Verification
09/30/04Accellera Re-elects Officers, Cites Progress in IEEE
more articles

Cadence feature stories



10/15/03Cadence Embraces SystemVerilog
02/24/03New Cadence Incisive™ Verification Platform Compresses Overall Verification of Nanometer-scale Designs by Up to 50 Percent
02/03/03It's About Time—Requirements for the Functional Verification of Nanometer-scale ICs