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Property Specification Language (PSL)

PSL supports today's popular RTL description languages, Verilog and VHDL, as well as IBM's internal environment description language, and it includes multiple abstraction layers for assertion types ranging from low-level boolean and temporal to higher-level modeling and verification. There is also a working group that is developing an implementation of PSL for use with SystemC®.

At its lowest-level, PSL uses references to signals, variables and values that exist in the design's conventional HDL description. By doing this, rather than employing a proprietary syntax, PSL ensures that each component's full range of behavior will be consistent, and apparent to various industry-standard verification tools, as the component moves through the design chain.

What's new

Introducing the Open Verification Methodology (OVM) SystemVerilog
Cadence and Mentor standardize on a tool-independent solution promoting data portability and interoperability.

OVM Recognized by Electronic Design magazine
SystemVerilog methodology named a Best EDA Technology for 2007.

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PSL (Sugar) consortium

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