Verilog
Verilog is the incumbent de facto and IEEE standard (IEEE 1364-2001) for RTL design. It has been in widespread use since the 1980's and is supported by all major EDA vendors. It is the basis for most logic synthesis tools and it provides good support for ASIC design and verification of simple and moderately complex chips. The limitations of Verilog became apparent in the late 1990's as the growing complexity of designs mandated better solutions for verification and increased abstraction levels for effective design and modeling. Verilog remains the language of choice for a broad cross-section of today's' designers who are not involved in cutting edge projects or who use it as an implementation language in a Multilanguage design and verification flow.
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