If you're having trouble reading this message, please click here.
Header

WHAT'S HOT

• Cadence DFM - WYDIWYG; Interview with Mike McAweeney »
• New Cadence Flow Enables Fast, Accurate Design and Manufacturing of Advanced ICs »
• Online product demos available »

separator

CUSTOMER ENDORSEMENTS

• Epoch Improves Accuracy Using Cadence RF Design Methodology Kit »
• "Virtuoso Passive Component Designer provides an easy way to model and generate PDK components" Hisaharu Miwa, general manager of the Design Technology Division, Renesas Technology Corp »

separator

SUBSCRIBE
Get on the mailing list of this quarterly newsletter.
More »

FEEDBACK
We'd like to hear your comments or questions about this newsletter.
More »
December 2007 Volume 5, Issue 4    

  Highlights in this issue:
  • CDNLive! webinar series »
Don't miss Cadence experts at upcoming events:
  • December 11, 2007 Using Virtuoso Spectre RF Noise-Aware PLL Methodology to Predict PLL Behavior Accurately — PEOPLE'S CHOICE
  • December 12, 2007 Virtuoso AMS Designer Migration, Usability and Performance Improvements
  • Cadence wants your feedback. What are your top custom design challenges? What product enhancements will help you overcome these challenges? Complete your top care-abouts survey today »
  • Circuit Simulation-Driven Analog/RF System-in-Package Webinar Series »
  • 12/13/07 Designing Off-Chip IC Package/SiP-Level Passive Structures Using Virtuoso and SiP RF Technology
  • 1/24/08 Advanced Techniques for IC Package/SiP Parasitic Extraction/Modeling and Backannotation for Circuit Simulation Using Virtuoso ADE and SiP RF
  • 4/8/08 Top-Down Design and Circuit Simulation of Analog/RF Systems-in-Package Using Virtuoso and SiP RF Solutions
   Platform news
12/03/07  UMC Foundry Design Kit for New Cadence Virtuoso Platform Speeds Production of 65nm Designs »
11/12/07 Cadence Announces New RF Technology to Ease Design of Nanometer Wireless Chips »
09/18/07 RFIC Solutions Achieves 2X Increase in Productivity with Cadence Virtuoso Platform »
  Get the complete news on the Virtuoso custom design platform »
   Articles
  • Cadence DFM - WYDIWYG; Interview with Mike McAweeney »
  • Signoff for Manufacturability: An absolute necessity at 45nm, Chin-Chi Teng and Rahul Deokar, Cadence Design Systems, Inc »
   Whitepapers
  • Chip Design Using 45nm Processes Requires a Holistic Approach to Planning and Implementation »
  • Model-based Methods Critical for Effective Manufacturing-aware Physical Design »
  • Next-Generation Signoff Analysis Tackles Electrical, Physical, And Manufacturing Challenges »
  • Automated Full-Chip Hotspot Detection and Removal Flow for Interconnect Layers of Cell-Based Designs »
  • AMD/Clear Shape: Automated Full-Chip Hotspot Detection and Removal Flow for Interconnect Layers of Cell-Based Designs »
    View complete list of white papers related to custom IC design »
   Events
  • CDNLive! webinar series »
Don't miss Cadence experts at upcoming events:
  • December 11, 2007 Using Virtuoso Spectre RF Noise-Aware PLL Methodology to Predict PLL Behavior Accurately — PEOPLE'S CHOICE
  • December 12, 2007 Virtuoso AMS Designer Migration, Usability and Performance Improvements
  • Circuit Simulation-Driven Analog/RF System-in-Package Webinar Series »
  • Circuit-Simulation-Driven RF/Analog System-In-Package Design »
  • Interfacing With the IC Package Design Team Using Virtuoso and SiP RF Architect
  • Circuit Simulation of Analog/RF ICs with IC Package Interconnect Using Virtuoso ADE and SiP RF
  • DVCon 2008-February 19 – 21, 2008 – San Jose, CA Session Number: 7.3: Paper Title: Analog Mixed-Signal Verification: Can modern approaches replace the traditional way? »
  • Microprocessor Test and Verification workshop December 5-6, 2007 in
Austin, TX »
   Cadence Designer Network User Community
Join other Virtuoso technology users around the world to exchange ideas and solve challenges. Below is a sample of what's new.
  • Virtuoso Passive Component Designer Now Supports Synthesis for Customer Pcells, Bo Wan – Cadence Design Systems »
  • Using Thermal analysis as a Tool to Aid Analog Floorplanning, David Schwan – Sirenza Microdevices »
  • Using Spectre RF Noise-Aware PLL Methodology to Predict PLL Behavior Accurately, Helene Thibieroz – Cadence Design Systems »
  • Automated Full-Chip Hotspot Detection and Removal Flow for Interconnect Layers of Cell-Based Designs, Ed Roseboom – AMD; Philippe Hurat – Cadence Design Systems »
  • Read more custom design articles and post to the forums.
   Cadence RF Methodology Kit
The Cadence RF Design Methodology Kit has features and benefits that provide:
  • System conformance validation of the RFIC through MATLAB/Simulink co-simulations
  • Complete spiral inductor synthesis through an electromigration verification flow
  • Full-chip verification through new "local" envelope technique
  • Noise distribution analysis and quick prototyping of noise isolation schemes
  • Complete PLL simulation guide
   Training & Education Services
Check out the latest class offerings, which include the easy-to-use, integrated design environment of the new Virtuoso custom design platform (6.1 release). See our online catalog:

Behavioral Modeling with Verilog-AMS 2.2 (Engineer Explorer series)
Updated for use with IUS6.1.1 and IC5141USR5. This course in our Engineer Explorer (EE) series shows advanced users how to write complex behavioral models using the Verilog-AMS language.

Analog Modeling with Verilog-A 6.2
This is an update to version 6.2 for use with MMSIM6.2 and IC5141USR5. This course introduces the Verilog-A language as a modeling language for analog behavior. Analog cells written in Verilog-A can be switched into designs to replace schematics for faster simulation.

Virtuoso AMS Designer 5.7 internet Learning Series(iLS)
iLS courses are on-line courses offered by Cadence Education Services. This version updates the previous version to 5.7 for on-line students. AMS Designer is a mixed-signal, mixed-language simulator for large designs, including use models with ADE and with UltraSim. The course also provides an introduction to the Verilog-AMS and VHDL-AMS modeling languages.

Assura Verification 3.1.7 (with IC 6.1.1)
This three day course has been updated to Assura 3.1.7 and is now based on the new IC 6.1.1 Virtuoso Design Environment using OpenAccesss. New ERC functionality is presented in addition to the user level DRC, LVS and ERC functionalities.

Unsubscribe
Cadence respects your online time and privacy.
To unsubscribe from all future Cadence email communications, please reply to this message and type "UNSUBSCRIBE" in the subject line.

Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134