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WHAT'S HOT

• Techtorial: Bridging the Gap Between RF IC, Package, and Interconnect RF IC Design Through an Integrated RF IC / SiP
Flow »
• Cadence Integrates SiP Technologies Into Latest Custom and Digital Design Flows »
• Online product demos available »

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CUSTOMER ENDORSEMENTS

"As a user of both Virtuoso and SiP technology, it's important to have the best integrated overall solution and flow. The latest SiP 16.0 technology delivers new levels of integration and design productivity that we need in order for us to deliver leading-edge multi-chip package solutions to our customers."

Christian Caillon
Engineering Director, Cellular Communication Division
STMicroelectronics

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September 2007 Volume 5, Issue 3    


  Highlights in this issue:
  • CDNLive! Silicon Valley 2007 is almost here – register now! Network with other custom design experts, attend paper/panel sessions (a few examples below), see the latest enhancements to the Virtuoso® platform, and hear product roadmaps. »
  • Smart and Enhanced Layout Parameterized-Cell Validation Tool Using Cadence-Based Language - STMicroelectronics
  • An Evaluation of ITDB Implementations - Freescale Semiconductor
  • CDB to OA - The Migration Report - austriamicrosystems
  • A Novel ESD Verification and Debug Platform - National Semiconductor Corporation
  • IBM z-Series Microprocessor and Cache Subsystem Chips Use Cadence Space-Based Router to Drive Multi-Gigahertz Design Point - IBM
  • Learn how driving an Analog/RF system-in-package module implementation from a single top-level schematic enables full pre- and post-route circuit simulation. Register for the webinar today! »
   Platform news
07/18/07  Toumaz Technology Achieves First Silicon Success With Cadence Virtuoso Multi-Mode Simulation »
7/11/07 Cadence Extends Integrated SiP Technologies into the Latest Custom and Digital Design Flows »
06/27/07 INSIDE Contactless Adopts Cadence Virtuoso Multi-Mode Simulation to Speed SoC Design Verification »
06/26/07 TSMC and Cadence Collaborate on 65-Nanometer Design Flow for Wireless Designs »
  Get the complete news on the Virtuoso custom design platform »
   Articles
07/30/07 Challenges at the 45nm Node are Great »
07/19/07  Analog/Full-Custom Flows Move Toward Interoperability »
   White papers
View complete list of white papers related to custom IC design. »
   Events
CDNLive! Silicon Valley 2007
CDNLive! Silicon Valley 2007 is almost here! Network with other custom design experts and see the latest enhancements to the Virtuoso platform, including product announcements and roadmaps.
More »
Techtorial
Bridging the Gap Between RF IC, Package, and Interconnect RF IC Design Through an Integrated RF IC / SiP Flow
Register »
Webinar
Circuit Simulation-Driven RF/Analog System-in-Package Design
More »
Archived webinars
Cadence Simulation and Verification Webinar Series Available on Demand »
Virtuoso Multi-Mode Simulation Enables Fast and Accurate Simulation and Verification. Topics include analog block design in 65/45nm, verification of mixed-signal SoCs in 65/45nm, wireless SoC and SiP verification, and verification of digital SoCs and memories in 65/45nm.
   Cadence Designer Network User Community
Join other Virtuoso technology users around the world to exchange ideas and solve challenges. Below is a sample of what’s new.
  • Utility for Extracting and Highlighting Net Connectivity in Virtuoso, Derek May - Micron Technology »
  • CDB to OA—The Migration Report, Gernot Heiling – austriamicrosystems (Winner of the Custom IC Best Paper Award at CDNLive! EMEA »
  • Read more custom design articles and post to the forums.
   Cadence Kits For The Virtuoso Platform
Foundries support Cadence Methodology Kits:
  • Cadence and SMIC Collaboration Validates RF Design Kit for Wireless IC
Design »
  • Jazz Semiconductor Teams with Cadence on Support for Cadence RF and AMS Design Kits »
   Training & Education Services
We've redesigned our entire curriculum around the easy-to-use, integrated design environment of the new Virtuoso custom design platform (6.1 release). Now available in our online catalog:
Virtuoso Connectivity-Driven Layout
This new IC 6.1 course covers the techniques for working with designs in the Virtuoso Layout Suite XL environment. The schematic-to-layout capability is used to generate and maintain layout designs that match the device sizes and parameters specified in the schematic. Options for setting up pin connections as well as how to use the new utility for configuring the physical hierarchy are covered.

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