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June 2007 Volume 5, Issue 2    

  Highlights in these issue:
  CDNLive! Silicon Valley registration now open! Network with other custom design experts, see the latest enhancements to the Virtuoso platform, and hear product roadmaps »
  New Virtuoso Multi-Mode Simulation Enables Fast and Accurate Verification of Designs Across Analog, RF, Custom Digital, Memory, and Mixed-Signal Domains feature story »
  Sign up for the Cadence Simulation & Verification Webinar Series! New Virtuoso Multi-Mode Simulation Enables Fast and Accurate Topics include analog block design in 65/45nm, verification of mixed-signal SoCs in 65/45nm, wireless SoC and SiP verification, and verification of digital SoCs and memories in 65/45nm »
   Platform news
06/06/07  Cadence QRC Extraction Tool First To Qualify On TSMC's 45nm Process Technology »
05/15/07  Cadence Introduces Industry's First Complete Custom IC Simulation and Verification Solution »
04/17/07  ASE Chooses Cadence for SiP Design Worldwide »
04/11/07  Cadence Space-Based Router Wins EDN Innovation Award for Electronic Design Automation »
  Get the complete news on the Virtuoso custom design platform »
   Articles
4/12/07  Efficient Computing and Advanced Visualization Accelerates Electronic Design »
  Whitepaper
Virtuoso UltraSim Full-Chip Simulator Netlist-Based EMIR Flow »
  Cadence Kits for the Virtuoso Platform
The Cadence AMS Methodology Kit cuts the time required to create complex analog/mixed-signal designs and helps to ensure first-pass silicon success.
The Cadence RF Design Methodology Kit enables customers to rapidly develop wireless designs by addressing system-level, verification, and IC parasitic challenges.
  Training & Education Services
We've redesigned our entire curriculum around the easy-to-use, integrated design environment of the new Virtuoso custom design platform (6.1 release). Now available in our online catalog:

Virtuoso Design Entry and Basic Simulation: Effectively create and edit schematics for use with the full suite of Virtuoso simulation and layout products. This new course covers Virtuoso Analog Design Environment L capabilities, from basic part construction and wire placement to advanced multi-sheet design, hierarchical design, component description format (CDF) editing, and basic simulation techniques.

Virtuoso Analog Simulation Techniques: This new course follows Virtuoso design entry and basic simulation. You will use Virtuoso Analog Design Environment XL for more complex simulations and learn more advanced techniques such as sweeps, corners, Monte Carlo, and designing to specifications.

Virtuoso Layout Design Basics: This new course covers the basic techniques for working with designs in the Virtuoso Layout Suite L environment and introduces the new user interface and assistants. Create and edit cell-level designs, and create and place instances, to build hierarchy for custom physical designs.

  Upcoming events
Sign up for the Cadence Simulation & Verification Webinar Series!
Topics include analog block design in 65/45nm, verification of mixed-signal SoCs in 65/45nm, wireless SoC and SiP verification, and verification of digital SoCs and memories in 65/45nm.
More »

CDNLive! Silicon Valley 2007
CDNLive! Silicon Valley registration now open! Network with other custom design experts and see the latest enhancements to the Virtuoso platform, including product announcements and roadmaps.
More »

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