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CDNLive! is a global series of technical conferences that bring customers together for face-to-face interactions. At CDNLive! Silicon Valley 2006 (September 12-14), you'll have the opportunity to talk with other designers using Cadence technology—and with the Cadence people who develop the technologies—to help you face your design challenges.
Register early and save!
2-for-1 early registration for $695 starts June 12

The Cadence Designer Network steering committee is pleased to announce the launch of an enhanced user community website

Registered members from the former Virtuoso community are registered automatically for this new community; your username and password are preserved. Technical papers, customer interviews, and forum postings have all been migrated to the new user community.
Visit today and find enhanced features such as member-contributed product reviews and product demonstrations.

Saifun Semiconductors Adopts Cadence Analog Mixed-Signal Methodology Kit

Agere Systems Standardizes on Cadence Virtuoso and Incisive Palladium Technologies to Speed Time to Market for 90- and 65-Nanometer Semiconductors

Cadence Virtuoso Platform Speeds Time to Market for Zarlink's Ultra Low Power SoCs

SMIC and Cadence Deliver New Analog Mixed-Signal Reference Flow to Speed Fabless Chip Design

Renesas Technology Gets Up to 2x Design Productivity Increase with Cadence Virtuoso NeoCircuit

Cadence Virtuoso Platform Provides 10x Improvement in Verification Time for VIS

Encrypting Process Information for Litho-Aware OPC Models

A Balanced Approach to Chip Optimization

Cadence CTO: CAD “Foundations” Must Change

Analog to Reach New High in 2006

Lithography Awareness Reaches Front-End Design Tools

Full-Chip Optimization Tool Boosts IC Yield and Performance

The Cadence RF Design Methodology Kit addresses key RF challenges:

• Intelligently manage parasitic extraction
• Link system-level design with IC implementation
• Accurately and rapidly verify complete wireless designs
  

New course now available from Cadence Education Services

• Virtuoso Digital Implementation Option 5.2

Our Engineer Explorer series offers advanced training for experience engineers. Currently available:

• Behavioral Modeling with Verilog-AMS
• SKILL Programming for IC Layout Design

Sequoia and Cadence develop world-class new RF transceiver architecture
View video »

NemeriX and Cadence team up to produce industry-leading GPS chipset
View video »

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