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The
Cadence® Virtuoso® custom design platform eNewsletter
keeps you informed about important issues, technology updates,
and solutions in analog, custom-digital, RF, and mixed-signal
design. This forum strives to address custom design challenges
that are relevant to your needs, so please feel free to share
your feedback with us at: virtuoso@cadence.com. |
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The Virtuoso custom design platform—delivering silicon
that's right, on time
Teams working on advanced custom designs face a triple threat—economics, design complexity, and physical effects. In today’s market, competitive design requires a fast, silicon-accurate custom design platform that addresses these issues. To view an interactive presentation on this topic, please go to:
www.cadence.com/virtuoso
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Design
Kits Target WLAN, Consumer Electronics Applications
Cadence recently unveiled its first offerings in what the company
calls its “kits approach” to streamlining design
capabilities for applications within the markets for WLAN, PCI
Express, Ethernet, and digital TV devices. |
Cadence,
UMC Develop Reference Design for Wireless
Cadence
and Taiwan-based semiconductor foundry UMC have announced a
collaborative agreement to develop a comprehensive reference
solution for complex wireless designs. |
Kits
Address Analog and Mixed-signal Design Challenges
Cadence announced the first offerings in its kits approach to
addressing designers' needs. The analog/mixed-signal (AMS) methodology
kit targets designers of wireless, wired, and consumer electronics
devices, allowing them to achieve shorter, more predictable
design cycles while creating reusable AMS blocks.. |
Fister
“Passionate” About Kits
Platform-based design was introduced several years ago as a
concept that would revolutionize chip design and redefine the
future of systems-on-chip. |
Multi-processing
Speeds IC Physical Verification
With
each step to more advanced process technologies, designs comprise
larger numbers of process layers and transistors per die, and
require more design rule checks before manufacturing handoff. |
Cadence
Officially Jumps Back into DRC/LVS
Cadence
is making another attempt to recapture the IC physical verification
market, as it officially unveiled its new DRC/LVS (design rule
checking, layout versus schematic) product: the Cadence Physical
Verification System. |
Cadence
Speeds IC Physical Verification
Promising a "massively parallel" approach to IC design
rule checking (DRC) and layout versus schematic (LVS), Cadence
rolled out its Physical Verification System for designs at 90nm
and below.
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WHITE PAPERS |
Cadence
Physical Verification System
The
new Cadence Physical Verification System implements a massively
parallel data processing approach that accelerates design signoff
by orders of magnitude compared to conventional tools. The system
delivers error data concurrently, during runtime, directly into
an interactive debug environment based on the Virtuoso platform.. |
AMS
Top-level Flow
This
document describes the AMS top-level flow to the Virtuoso platform.
The flow is based on the ACD methodology and is one flow element
of the Virtuoso platform. Its scope is defined as top-level
simulation and analysis, and it works closely with the AMS block
creation and analog-driven physical implementation flows. |
Analog
Block Creation Flow with Reuse and Migration Flow
Creating
AMS and analog IP is traditionally more an art form than a repeatable
process. Yet today’s complex ICs, and the ever increasing
need for efficiency due to tight design schedules and a shortage
of analog engineers, makes it paramount to allow others to leverage
IP and reuse as much as possible. |
Analog-driven
Physical Implementation Flow
This
paper describes the analog-driven physical implementation flow
in the Virtuoso platform. The flow accepts IP across multiple
design domains to provide a physical design integration solution
for mixed-signal macrocells through large mixed-signal SoCs,
and it encompasses floorplanning through tapeout.
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VIRTUOSO
COMMUNITY |
Check
out the user community for analog, RF, and mixed-signal
designers. Share and contribute information on best practices
for solving today’s custom design challenges. This extensive
resource center features technical content on how to design
faster and more accurately, as well as design tips and work-arounds—all
organized by design type.
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CADENCE AMS METHODOLOGY KIT |
The
new Cadence AMS Methodology Kit addresses key analog/mixed-signal
design challenges:
Verifying designs across analog and digital domains
Modeling, extraction, and re-simulation of parasitics
Management of multiple power supplies
Reuse and migration of mixed-signal blocks
View
more information »
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CADENCE
ENGINEERING SERVICES |
Cadence
Engineering Services
can help you meet your broader business and project goals by
collaborating with you on the appropriate choice of flows; offering
design expertise; and enabling IP, and developing partnerships.
Each services engagement is tailored to your specific design,
budget, and schedule requirements.
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TRAINING
& EDUCATION SERVICES |
Cadence
Education Services has two new offerings:
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Behavioral
Modeling with Verilog-AMS 1.0
This new Engineer Explorer course provides an in-depth
approach to behavioral modeling of analog and mixed-signal
design blocks and systems. In this advanced course, you
will learn how to create parameterized Verilog-AMS models
for analog/mixed-signal blocks, and verify the functionality
and performance using Virtuoso AMS Designer Simulator.
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Simulation
and Analysis Using OCEAN
This new course provides an introduction to the OCEAN
scripting language and its use in the Virtuoso Analog
Design Environment. Through the use of operational and
programming labs, you will explore the use of OCEAN to
run analog and mixed-signal simulations and to manipulate
simulation results.
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| WHAT'S
NEW |
| Check
out the new technical paper on the Cadence Physical Verification
System, which implements a massively parallel data processing
approach that accelerates design signoff. Its performance scales
linearly and is limited only by the compute resources available |
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Missed
DAC? You can learn more about these Virtuoso custom design
flows:
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RF
IC wireless design flow that enables better parasitics
management and multi-domain verification |
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New
AMS block-level design flow that accelerates AMS design
and verification |
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| FEEDBACK |
We'd
like to hear your comments or questions about this newsletter.
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