Cadence 2008 Technology on Tour,結合了最先進的Cadence產品和最佳化的設計流程,精心為您打造最佳的技術解決方案。您可與Cadence技術專家們面對面進行交流,並體驗最新的產品Demo
Cadence “Technology-on-Tour”
向您介紹最新的設計技術與設計方法,藉由產品DEMO和廣受歡迎的技術演說,讓您對Cadence技術與解決方案有更深入的認識,協助您設計出高性能、低功耗的晶片和系統,提高設計產能、改善良率,以及縮短產品上市時程。並通過與其他設計人員交換設計經驗,您可以發現全新解決方案。
機不可失,現在就報名Cadence “Technology-on-Tour”!!!

 

  • Si2標準 CPF(Common Power Format)為基礎、唯一經過量產驗證的低功耗晶片設計解決方案以及客戶成功案例
  • 最新以SystemVerilog為基礎的開放式驗證方法 (Open Verification Methodology,簡稱OVM)”
  • 針對先進製程可製造性設計(DFM)的挑戰與解決方案
  • 最新一代針對SoC晶片驗證的高速硬體加速與模擬技術
  • 針對客製化晶片模擬與驗證環境的新突破

 

  • 數位IC設計與驗證工程師與管理人員
  • 類比與混合訊號IC設計與驗證工程師與管理人員
  • PCB與系統設計工程師與管理人員
  • CAD工程師與管理人員

 

2008722 (星期二)
活動時間
: 09: 00am – 16:30pm
活動地點: 新竹國賓大飯店 10F
電話:               03-515-1111       
地址: 新竹市中華路二段188
交通方式
: http://ambassador-hisnchu.network.com.tw/traffic.asp
*
與會者可於會後領取國賓飯店免費停車券

7:30am 台北火車站東三門 -> 新竹國賓大飯店
5:00pm
新竹國賓大飯店-> 台北東三門

9:00-
9:30

Registration

9:30-
9:35

Welcome

Welcome by Willis Chang, Country Manager of Cadence Taiwan

9:35-10:05

Keynote

2008: A Challenging Yet Promising Year for Asia Semiconductor and Electronics Market, Lung Chu, Corporate VP and President of Asia Pacific

10:05-10:35

Keynote

Guest Keynote: Philip Lu, Country Manager, ARM Taiwan

10:35-11:25

Keynote

Co-presentation: Economic Impact of Green Electronics – Why Does It Make Economic Sense to Design Low Power Chips
(C.J. Hsieh/Faraday; Frank Leu/Cadence; modertor: Janet Wang/Compotech) 

11:25-11:30

 

All attendees proceed to breakout rooms

11:30-12:00

 

Topic

Speaker

Title

Front-end Closure

Break-out Keynote

Metric Driven Verification for Full Chip SoC Verification

Apurva Kalia

Corporate VP - 
System and Functional Verification, Cadence

Low Power

Break-out Keynote

The Cadence Low Power Solution and Common Power Format: Enabling Next-Generation Low Power Designs

Frank Leu

Corporate VP - ICD R&D, Cadence

Advanced Node

Break-out Keynote

Cadence DFM Solution Overview

Jason Huang

MMI Product Engineering Director

AMS Design

Break-out Keynote

Whats New about Virtuoso 6.1.3?

Kevin Tsai

AE Manager

Package and PCB Design

Break-out Keynote

Package and PCB Design Trend, Challenges and Solutions

Tric Chiang

Regional Technical Marketing Manager

12:00- 13:30

Lunch

13:30-14:15

 

Topic

Speaker

Title

Front-end Closure

Presentation

Developing a SystemVerilog Verification Environment with OVM

YS Lin

AE Leader, Incisive, Cadence

Low Power

Presentation + Demo

Encounter Test Updates

Anis Uzzaman

Sr. Product Engineering Manager

Advanced Node

Presentation

 Encounter DFM Overview

Nora Chu

Sr. Product Marketing Manager

AMS Design

Presentation

Boosts Performance with Full SPICE Accuracy with Spectre Turbo

Michael Tian

Engineering Director of the Virtuoso Spectre R&D Team, Cadence

Package and PCB Design

Presentation

HDI and IC Substrate 的現況及未來發展趨勢 (PCB教父 白蓉生)

Frank Pei

TPCA

14:15-15:00

 

Topic

Speaker

Title

Front-end Closure

Demo

Enable Schedule Predictability, Resource Utilization and Productivity with ePlanner/eManager

Simon Chang

Regional AE Manager

Low Power

Demo

Maximize your design performance by optimizing SDC timing constraint, with new MCC technology from Conformal Constraint Designer

Andy Lin/
Da-Ching Chen

Vice President of Conformal RD/Sr. Product Engineer

Advanced Node

Demo

QRC Updates

Richard Lee

Sr. Technical Marketing Manager 

AMS Design

Presentation

Virtuoso RF Designer - Full Wave EM Synthesis and Analysis

Bob Mullen

Technical Marketing Director

Package and PCB Design

Demo

Increasing the system Performance and Form Factor - SiP RF Design

Charlie Shih 

Regional Application Engineer

15:00-15:15

Break

15:15-16:00

 

Topic

Speaker

Title

Front-end Closure

Demo

Experience Power and Speed of Hardware-assisted Verification capabilities: Xtreme-III

Gerald Lo/
Simon Chuang

AE

Low Power

Demo

Accurate Sign-off Analysis for Complex Low-Power Designs with VoltageStorm

Jason Huang/ Tom Taylor

AE/Product Engineering, ICD Analysis, Cadence

Advanced Node

Demo

Insight of Cadence LPA and LEA and successful Experience Sharing

Nail Tang

Product Engineer, MMI, Cadence

AMS Design

Presentation

New Challenges in Advanced Device Modeling for 65nm and Beyond

Dr. James Ma

President & CEO, ProPlus Design Solutions, Inc

Package and PCB Design

Demo

Cadence MGH (multi-gigahertz) Design

Joseph Kao

Sr. Application Engineer

16:00-16:30

Wrap up & Lucky Draw 

報名方式: 一律線上報名
報名網址: http://www.cadence.com.tw/

http://www.cadence.com.tw/event/tot2008/signup.php?lists=37

活動聯絡人: 請洽您的公司業務代表,或請洽:
沈瀅渝 (Sophy Shen)
電話:               03-566-3834       
Email: sophys@cadence.com

來參加者就有機會獲得 "威秀影城" 電影票兩張,

參與腳踏車比賽更可以得到紀念品一份!
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