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December 2007 Volume 6, Issue 4    


  Highlights in this issue:
  • New! Improved performance and productivity in next-generation Incisive Enterprise Verification Family:
  • The latest on the Open Verification Methodology (OVM) for SystemVerilog:
  • Technical tips and tricks from users:
   Platform news
12/3/2007  Cadence Boosts Performance and Productivity of Enterprise Verification Engineers »
11/28/2007  Micronas Selects Cadence Incisive Plan-to-Closure Methodology for Verification Planning »
10/15/2007  Anchor Bay Adopts Cadence Incisive Xtreme III System for Verification of HDTV and Digital Video Products »
  Get the complete news on the Incisive functional verification platform »
   Articles
12/10/2007 Implementing Error Injection Capabilities in the Verification Environment »
12/10/2007 Verifying Checkers in an e Verification Component (eVC) »
12/4/2007  Accelerating Simulation While Preserving a Familiar Verification Environment »
11/19/2007  I Know What You Didn't Verify Last Summer! »
11/05/2007  Design with Verification: Not an Oxymoron »
   Cadence Design Network User Community
Join other Incisive technology users around the world to exchange ideas and solve challenges. Below is a sample of what's new:
• CDNLive! 2007 SiliconValley best paper awarded to Kelly D. Larson from Analog Devices for "Translation of an existing VMM Testbench into URM"
• Interview with Erik Panu and Mike Stellfox from Cadence: Closing in on Profitability with Leading-Edge Verification Practices
• Simplifying Vertical Reuse with Specman Elite—Mark Strickland, Cisco Systems
• Low-Power Design and Verification using CPF—Milind Padhye, Freescale Semiconductor
• Metric-Driven Methodology Speeds the Verification of a Complex Network Processor—Jean-Paul Lambrechts, Cisco Systems
Read more functional verification articles and post to the forums.
   Archived Webinars
Incisive Plan-to-Closure Methodology Technical Webinar Series »
Complex Chip and SoC Verification Guide from Plan-to-Closure »
Leveraging Verification Planning & Management to Reduce Overall Risk—Get More Viability and Control Over the Verification Process »
Increase Productivity Using Complete Assertion-based Verification Environments »
Incisive Verification for RTL Design Teams; Incisive Verification for Multi-specialist SoC Project Teams »
   Training & Education Services
Training classes are now available for the majority of the Functional Verification technologies. They are being scheduled and offered in Cadence Training Centers. See a full list of classes.

New and Update Releases
• SystemVerilog Language and Application, version 6.1
• C++ Introduction for SystemC Users, v. 6.1
• Incisive Simulator Assertion Based Verification (ABV) Using PSL, v. 6.1
• Specman Elite Basics for Verification Environment Users, v. 6.1.1
• Specman Elite Basics for Verification Environment Developers, v.6.1.1

Coming Soon
• Simulation and Verification of LowPower Designs with Incisive Unified Simulator, v. 6.1.1
• SytemVerilog Module-Based Plan to Closure Methodology, v. 6.2
• Formal Analysis with Incisive Formal Verifier, v. 2.1

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