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UPCOMING EVENTS

CDNLive! Silicon Valley
September 10 - 12, 2007
San Jose, CA
Conference details »

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August 2007    

  Highlights In This Issue:
 
CDNLive! Silicon Valley 2007 coming soon! Register today!
September 10 - 12, 2007
San Jose, CA
Here’s a glimpse of what’s in store for you at CDNLive! Silicon Valley 2007:
Technical presentations and panels:
  • The future of SoC verification, moderated by Ron Wilson from EDN Magazine
  • Power-aware verification
  • The latest verification successes
     
Technical workshops featuring Plan-to-Closure-based methodology:
  • New SoC Functional Verification Kit
  • Logic design with verification
  • Full enterprise system-level (ESL) verification solutions
  • The latest in SystemVerilog
     
Product demonstrations:
  • Acceleration and emulation-based technology
  • Comprehensive coverage techniques
  • The Universal Reuse Methodology (URM) mixing e and SystemVerilog languages
  • Verification IP development
     
Special event at CDNLive!
    Plan-to-Closure Community Reception
    Tuesday, Sept. 11
    5:15pm – 6:00pm
    San Jose Convention Center, Meeting Room D
     
  • Introducing the Open Verification Methodology for SystemVerilog »
  • New Cadence SoC Functional Verification Kit Cuts Overall Verification Development Effort »
  • Plan-to-Closure Methodology reduces verification risk — in any language »
 
   Articles
  • Hardware Based Acceleration Technology Moves to Mainstream »
  • Effective Verification Management: Tools For Herding Cats »
  • Huge Gains in SystemVerilog Support with 6.1 »
  • A robust coverage driven verification methodology for a Hard Disk Controller (HDC) System »
  • Taking Full Advantage of the Metrics at Hand to Improve your Verification
Process »
  • How to Use SystemVerilog for Coverage »
  • STIL Verifier: Post-Silicon Functional Test Automation within the Incisive
Platform »
  • End-of-Test Mechanism in a URM SystemVerilog Module-Based Solution »
  • From Panic-Driven to Plan-Driven Verification »
  • Quick Take: Specman-Based Verification Methodology for Power Management
IPs »
  • Generating Stimuli for Layered Protocols using Sequences »
  • A Simple New Approach to Hardware Software Co-Verification »
  • Cadence Compliance Management System Enables ClearSpeed to Reach Coverage Goals Faster »
 
Incisive Plan-to-Closure Methodology Community Highlights
Plan-to-Closure Community Reception at CDNLive! Silicon Valley »
Date: Tuesday, Sept. 11
Time: 5:15pm – 6:00pm
Location: San Jose Convention Center

Join members of the Incisive R&D team, field technical personnel, and executives to have an informal conversation about the Incisive Plan-to-Closure Methodology, the component technologies, and the products that support this methodology. This is a great opportunity to talk directly with key Cadence R&D personnel as well as mingle and chat with other Cadence verification customers. The reception will start at 5:15 pm, right before Cadence Technology Night and will feature a selection of Hors d'Oeuvres.

Plan-to-Closure Knowledge System
The Incisive Plan-to-Closure Methodology includes a traditional print version of the methodology, and a web-based system that enables verification engineers to assemble and deploy the resources they need to speed adoption and customization of the methodology. The interactive Knowledge System, available with the Incisive Plan-to-Closure Methodology, enables widespread sharing of resources, including those provided by Cadence, internal users, and an external community. The Knowledge System supports both design and multi-specialist enterprise teams.

Preview Plan-to-Closure Methodology »
 
   Archived Webinars
  • Incisive Plan-to-Closure Methodology Technical Webinar Series »
  • Complex Chip and SoC Verification Guide from Plan-to-Closure »
  • Leveraging Verification Planning & Management to Reduce Overall Risk—Get More Viability and Control Over the Verification Process »
  • Increase Productivity Using Complete Assertion-based Verification
Environments »
  • Incisive Verification for RTL Design Teams;
Incisive Verification for Multi-specialist SoC Project Teams »
     

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