If you're having trouble reading this message, please click here.
Header

UPCOMING EVENTS

SystemVerilog Luncheon at DAC
Wednesday, June 6, 2007
11:30AM – 1:00PM
Register today »

CDNLive! Silicon Valley
September 10 - 12, 2007
San Jose, CA
Conference details »


separator

SUBSCRIBE
Get on the mailing list of this quarterly newsletter.
More »

FEEDBACK
We'd like to hear your comments or questions about this newsletter.
More »
May 2007    

  Advanced Verification Alert:
  • Welcome to the World of Incisive Software Extensions »
  • Quick Take: Specman-Based Verification Methodology for Power »
  • Specman-AMS Integration in Incisive Enterprise Simulator »
   Articles
    Editor's Note »
  1. Welcome to the World of Incisive Software Extensions »
  2. Quick Take: Specman-Based Verification Methodology for Power
Management IPs »
  3. Specman-AMS Integration in Incisive Enterprise Simulator »
  4. Enterprise System-Level (ESL) Verification Solution »
  5. Metric-Driven Methodology Speeds the Verification of a Complex Network Processor »
  6. New Protocols Supported Within the Cadence End-to-End Verification IP
Portfolio »
  7. Predictable Front-End Power and Closure »
     
   Incisive Plan-to-Closure Methodology Community Highlights
 

The Incisive Plan-to-Closure Methodology includes a traditional print version of the methodology, and a web-based system that enables verification engineers to assemble and deploy the resources they need to speed adoption and customization of the methodology.
Preview Plan-to-Closure Methodology »
   Upcoming events
 

SystemVerilog Design with Verification: Oil and Water Can Mix
Wednesday, June 6
11:30am - 1:00pm
San Diego Convention Center, Rooms 30CDE
Lunch provided
Register now »

Adopting a Plan-to-Closure Methodology Across Design Teams and Verification Teams
Presented by Doulos and Cadence Design Systems
Tuesday, June 5
12:45pm - 2:30pm
San Diego Convention Center, Room 27B
Lunch provided
Register now »

   
   Archived webinars
  •

Incisive Plan-to-Closure Methodology Technical Webinar Series »
  • Complex Chip and SoC Verification Guide from Plan-to-Closure »
  • Leveraging Verification Planning & Management to Reduce Overall Risk—Get More Viability and Control Over the Verification Process »
  • Increase Productivity Using Complete Assertion-based Verification
Environments »
  • Cadence Verification Solutions Webinar Series »
     

Unsubscribe
Cadence respects your online time and privacy.
To unsubscribe from all future Cadence email communications, please reply to this message and type "UNSUBSCRIBE" in the subject line.

Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134