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INCISIVE PLATFORM eNEWSLETTER
Q206

HIGHLIGHTS
•	New Cadence Incisive Enterprise Technology Eases Creation of Verification Scenarios Hear more about the latest addition to the Enterprise Family —- Incisive® Enterprise Scenario Builder. This exciting new technology eases verification with innovative natural visualization of the verification environment - enabling designers and verification specialists to create realistic chip-level scenarios in a matter of hours instead of days.
•	Risk on the Rise By Steve Glaser, Cadence Design Systems Electronic News, 3/27/2006 "Companies need to trust that the products they go to market with will be on schedule and bug free"…

PLATFORM NEWS

•	New Cadence 'Knowledge System' Speeds Adoption and Customization of Incisive Plan-to-Closure Methodology Check out this new Innovative Web-Based System that leverages Cadence, Customer and Community methodology resources that go well beyond manuals and libraries to enable widespread sharing of methodology resources. The three new components include Incisive Plan-to-Closure, My Plan-to-Closure and Community Plan-to-Closure-enable.
•	IEEE Ratifies first open 'e' language Standard for Verifiying Complex System-On-Chip Designs Check out the new standard from the IEEE addressing the challenges of verifying complex system-on-chip (SoC) designs from block to system levels. The standard, IEEE 1647tm, "Standard for the Functional Verification Language 'e'", is the first uniform, open e-language specification. The standard contains advanced constructs and facilities not found in other verification languages and is widely used by chip and computer makers the world over.
•	IEEE Recognizes Cadence Leadership and Contributions to IEEE 1800 SystemVerilog Standard IEEE has recognized Cadence® for its leadership and contributions to the IEEE 1800 SystemVerilog standard. Nine Cadence technologists received awards for a wide range of improvements during the development of the SystemVerilog standard.

ARTICLES

1.	Editor’s Note
2.	Verification Planning to Functional Closure of Processor-Based SoCs
3.	Incisive Assertion Library: Jump Start Assertion Based Coverage Driven Verification
4.	Incisive Enterprise Scenario Builder Increases Value and Verification IP Reuse
5.	System Validation: An In-Depth Comparison of FPGA Prototyping to Emulation at Sciworx
6.	e and SystemVerilog “Nibble” on the Plan-to-Closure Reuse Methodology
7.	Systematically Implementing Late Engineering Changes on Your Project – Do’s and Don’ts
8.	Are You Gambling With Your Designs?
9.	Using When-Subtyping Effectively in Specman Elite Verification Environments
	Download complete issue of Incisive Q206 Newsletter

WEBINARS

2006 Incisive Plan-to-Closure Methodology Technical Webinar Series

UPCOMING WEBINARS
Transaction-Based Verification
Date/Time: 06/14/06 - 10:00 AM PST
Presenter: Gary Hall
Description: This technical webinar will cover system-level verification and validation using Transaction-Level Modeling (TLM) and Transaction-Based Acceleration (TBA) methodologies. You will learn how to use SystemC to create TLMs and TLM and RTL Transaction Based Acceleration environments. Finally, we will show how the TLM can be used with TBA for complete Transaction-Based Verification flow.
Register now »

Assertion Based Verification
Date/Time: 07/19/06 - 10:00 AM PST
Description: This technical webinar will cover how to leverage assertions in the design and verification process. You will learn where to insert insertions and how to define them correctly. You will learn how to verify block functional correctness with assertions, without the need of testbench simulation. In addition this technical webinar will show how assertions used for block verification can be leveraged at the chip and system levels.
Register now »

ARCHIVED WEBINARS

• Incisive Plan-to-Closure Methodology Overview

• SystemVerilog Design Team Methodology

• Verification Planning & Management Methodology

• Mixed-Language Verification

• Cadence Verification Solutions Webinar Series — Incisive Verification for Multi-specialist SoC Project Teams

• Cadence Verification Solutions Webinar Series — Incisive Verification for RTL Design Teams

CUSTOMER ENDORSEMENTS

See what Verification Managers from Philips Semiconductor are saying about Incisive Xtreme Server
Read more »

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