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  In this issue of the Incisive® Newsletter, you'll get a closer look at technologies and methodologies that can enhance your verification environment and ultimately reduce risk in your design projects. We'll start by discussing the history of verification techniques and how you can take the next step in the evolution of verification. Following up on the previous newsletter's look at simulation acceleration and emulation techniques, we'll examine the technologies used to implement these techniques and explain how your choice of HW architecture can affect your goals. Next, we'll explore how formal assertion-based analysis technologies can be used not only to increase your verification coverage, but also to begin your verification much earlier in the design cycle. We've also included several articles that will introduce you to verification concepts including scalable performance, scalable testbench, and why mixed-language support is more important than ever.  


NEWS AND ANNOUNCEMENTS
On October 24, Cadence Design Systems, Inc. announced the segmentation of the Incisive® functional verification platform, including full solutions with tailored and integrated products coupled with methodologies for unique segment needs. The product families add additional support for multiple languages optimized for each specialist, including the most powerful, yet lowest risk, SystemVerilog-based offering. The three-tiered approach provides Cadence customers with optimal solutions tailored to specific levels of verification complexity. The three families are the Incisive Enterprise family, the Incisive Design Team family, and the Incisive HDL family.
More information »
ARTICLES
1 Modern Simulator Acceleration and Emulation Technology
2 Achieving Productivity and Quality Gains using Incisive Formal Verifier
3 Mixed Language Flexibility
4 Scalable Performance Technical Brief
5 Verification Management Technical Brief
6 Scalable Testbench Technical Brief
7 The Next Steps in Verification
 



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