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  Welcome to the Q3 edition of the Cadence® Incisive® Newsletter.
In this issue, learn about an important new event for the verification world – CDNLive! Hear how one company addresses the challenge of DFT for complex SoC designs, and ensures that their DFT efforts achieve their test intent. See how a customer evaluated assertion-based verification using PSL, and what they found. And find out what simulation acceleration, emulation, hardware prototyping, FPGA-based acceleration, processor-based techniques could mean for you. Examine the products, technologies, and techniques you can use to accelerate your verification process. Finally, learn how the “nchelp” utility can give details on error messages to help you solve your problem. Please share your feedback with us at: Incisive_info@cadence.com.


NEWS AND ANNOUNCEMENTS
Get the latest news»  
ARTICLES
1 Learn How to Reduce Your Verification Risk at CDNLive!
2 How are you planning to verify all that DFT?
3 Getting Help on Warning and Error Messages with the Incisive Unified Simulator
4 Evaluating PSL: A User Case Study
5 Keys to Simulation Acceleration and Emulation Success
 
EVENTS
We just completed a six-part webinar series that showcases 2005 Technology on Tour and DAC demos. Cadence technical experts presented the latest technology and integrated flows -- new capabilities that will help you design and verify higher-performance chips and systems, increase productivity, improve your yield, and speed your time to market.

This webinar series is now available as archives, use this opportunity to see the demos again or view demos that you may have missed.

2005 Technology on Tour and DAC demos Webinar Series:
- System Verification productivity from plan to closure
- Complete assertion-based verification
- Formal assertion verification on Designers Desktop
- Advanced verification environment
- Design and verification productivity with SystemVerilog
- First silicon with first software

Register and select the webinars you want to view»




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