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December 2007 Volume 6, Issue 4    


  Introducing Aspect Oriented Generation: New Generation Technology for a Billion Gate World
By Hannes Froehlich, Product Engineer,
Efrat Gavish, R&D Manager,
Corey Goss, Core Comp,
Incisive Technical Team
  Originally codenamed "IntelliGen", the new aspect-oriented generator for Cadence® Specman-Elite® provides new constrained random stimulus generation capabilities that deliver unsurpassed ease-of-use, functionality and performance over "Pgen", the current Specman-Elite generation engine. Constrained random generation is a cornerstone of the automated Coverage-Driven Verification (CDV) methodology and its superset, the Cadence Plan to Closure Methodology. As a result, this new engine will not only help you find bugs faster today but will also enable many future advanced verification products. Specifically, this new generator delivers the following benefits to users:

  • Improved Ease-Of-Use:
    • Generation is completely independent of variable ordering
    • Improved handling of constraint contradictions
    • All new GUI debugging environment
  • Improved Functionality:
    • Improved solvability of complex arithmetic and bit manipulation constraints
    • Improved solvability of hierarchical and list constraints
    • Improved coverage results due to better solvability and less order dependency
  • Improved Performance:
    • Up to 5x faster run time
    • Designed with scalability to handle generation constraints for the largest, most complex designs (over 1 billion logic gates)
    • Memory consumption that is scalable vs. environment size
    • New generation profiling features

This article will elaborate on the above benefits, using code examples and anecdotes where necessary.

Before diving into the aspect-oriented generator's new capabilities, it's worth saying a few words about the current Specman Elite generation engine, Pgen. When Pgen was first conceived (almost 10 years ago), one of the assumptions built into the engine was that users would be willing and able to use their knowledge of the DUT to guide the generator around known illegal areas using simple constraints. Back when the largest DUTs were 100,000 logic gates, this turned out to be a perfectly safe assumption. However, as design sizes regularly started to pass the 1 million gate mark, and as more customers began to receive IP from third parties, the problem space began growing beyond the point where it was obvious where illegal state spaces might be located, or even what higher-order contradictions might occur when combining two or more pieces of IP. Designs became increasingly elaborate, requiring complex sets of constraints to guide the Specman Elite generator into corner cases, yet away from illegal areas.

While Cadence has been able to continually enhance Pgen to meet the scalability requirements of verifying literally the largest chips in the world today, enhancing Pgen’s architecture to meet ever advancing memory consumption and wall-clock performance targets has become increasingly difficult. Furthermore, many customers have been signaling that it will not be long before they will need to verify DUTs with at least 1 billion logic gates (yes, 1 billion logic gates – not just transistors, and not counting the gates devoted to on-chip memory). As a result, roughly four years ago this month the decision was made to investigate all-new algorithms and architectures that would permit higher memory and wall-clock performance, unlimited scalability, and simplify the constraint specification and debug task for the end-user, regardless of the DUT size. The result of this effort – over 20 man-years of effort to be exact – is the new Cadence aspect-oriented generation engine. The remainder of this article will introduce the engine's capabilities in detail.

Improved Ease-Of-Use
To help keep the verification process manageable as its complexity increases, the aspect-oriented generator has been designed to make constrained-random generation more intuitive, and to simplify the constraint debug process. New ease-of-use features include:

  • Generation is completely independent of variable ordering
    The new generator applies a more integral approach to generation by first partitioning the system into sets of fields that are connected by constraints, and then solving all the connected fields in the same set at the same time. This approach makes generation results independent of the declaration order of generatable fields within structs or units, which results in:
    • Simplified generation semantics
    • Simplified generation code since generation ordering directives are now unnecessary
    • Improved random stability of the verification environment (i.e., the effect of adding new code will have minimal impact to generation results)
  • Improved handling of constraint contradictions1
    The new generator also provides much improved information on the generation process, making it easier to debug generation problems such as contradictions or unexpected values. When contradictions do occur during generation, valuable on-screen information is presented to the user to assist with rapid debug. For example:


    In addition to the on-screen information presented, users may also choose to set generation breakpoints and use the newly redesigned generation debugger to view generation results in a GUI window (see the next section for more details).
  • All new GUI debugging environment
    An all new Generation Debugger has been created to display much more information on the generation process, making it easier to debug problems such as contradictions, unexpected values, or inconsistent dependencies between variables. Users can now debug the generation process step by step just like using a procedural code debugger. The new Generation Debugger is also closely linked to the Specman source code debugger, allowing users to set breakpoints on generation actions within your environment and then step into, and through, the generation process.

    Consider the following screen shot:


    A detailed review is beyond the scope of this paper, but in short, on the left side of the "Gen Debug" GUI is a summary of environment fields that are somehow connected with each other via constraints. The fields together with their constraints are called "Connected Field Sets" (CFS2). The next debug step is to look inside a given CFS of interest, using the GUI to break down the CFS into parts and/or show the interrelationships between the constraints in the CFS. The bottom-line is that whenever a generation contradiction occurs, or the user is looking to clear a bottle neck in generation performance, this new visualization capability enables users to quickly zoom in on specific issues in order to resolve problems much faster than previous approaches.

Improved Functionality
The most complex generation schemes display a heavy interaction of constraints on many fields. This can be a result of a complex DUT (like multi-threaded, multi-pipeline micro-processors; or MPEG4 codecs), or due to the fact that the DUT comprises many interacting interfaces (such as complex SoCs with numerous internal busses). It is important that all generated fields are taken into consideration as a whole, together with their constraints. This is the reason the new generator introduces the concept of the CFS. The engine is able to generate all fields of a CFS together in a single generation cycle, thus increasing the solving power dramatically (not to mention this also provides the added benefit of improved performance). New functionality features include:
  • Improved solvability of hierarchical and list constraints
    The introduction of the CFS concept also improves handling of hierarchical constraints, since the CFS can contain fields from any point of the environment hierarchy. This allows for greater flexibility and control for many aspects of generation, especially for generating streams of input transaction objects using the powerful e Reuse Methodology (eRM) sequencing mechanisms.

    Lists are a popular modeling feature used in many verification environments. The new generator greatly improves solving of list constraints and also enables new constraint expressions such as:

    keep for each (m) in mylist {
    m < x + y; // where x, y are both random variables
    m > mylist[index-2];
    }; // keep for each (...
    keep mylist[3] == 10;
  • Improved solvability of complex arithmetic constraints
    The new generator adds enhanced inference and solving capabilities of various constraint types. This allows it to treat complex arithmetic constraints (multiplication, division) and bit-slice/bit-manipulation in a bi-directional fashion.
  • Improved coverage results due to better solvability and less order dependency
    Due to the fact the all fields which are related via constraints (CFS) are solved together, the engine generates much more uniform distributions of values, since variations on multiple fields are taken into consideration during one generation step. This allows users to achieve greater functional coverage faster, resulting in fewer tests written and reducing project schedules.

Improved Performance
There are many different ways to pull in a project schedule. Using the fastest, most efficient engine for a given task is a great place to start, and the generation algorithms inside the new aspect-oriented engine were designed with this time honored strategy in mind. Consider some of the new performance features:
  • Up to 5x faster run time
    Results from numerous beta program customers have validated that IntelliGen has excelled in improving wall-clock, run time performance. Our current roadmap is to enhance the performance of generator to permit up to 10X run-time improvement over Pgen.
  • Designed with scalability in mind to handle your most complex 1 billion logic gate designs
    For environment scalability, particularly for environments developed along eRM guidelines, the growth of resource consumption by the new engine increases linearly vs. the number of constraints in the environment. In short, this characteristic is targeted to address the requirement to stay well ahead of DUT growth, as they exceed the 300 million logic gate mark today, and will ultimately exceed the billion-gate mark within a few years. Translated into generation technology terms: the new Cadence engine is fully capable of handling user environments containing hundreds of thousands of constraints and tens of thousands of subtypes for items such as sequences. (One real-world example from the early adopter program is a customer that is starting to use the technology in a verification environment with over 250,000 lines of e code.)
  • Memory consumption that is scalable vs. environment size
    The aspect-oriented engine has been found to consume up to 10x less peak memory when compared to the current Pgen generation engine. One concrete example involving both memory and scalability involves the popular register-modeling package (the "vr_ad" UVC3) included as IP in the Cadence Plan-to-Closure Methodology package. As shown in the following figure, by varying the number of active registers in the vr_ad UVC we can objectively measure IntelliGen’s response. The largest such example in-house is one that instantiates and runs 10,000 registers while only consuming 390MB of memory. Other in-house testing suggests the average improvement in generation-related memory consumption to be an average of 2x better for heavily sub-typed environments.

  • New generation profiling features
    In addition to obtaining valuable performance information regarding methods, temporal expressions and coverage groups, you can now use the Specman profiler to identify CFSs that consume significant time or memory. Users can now easily streamline their constraints to obtain optimal performance.

In summary, the new Cadence aspect-oriented generator for Specman-Elite provides much improved ease-of-use, streamlined functionality and up to 5x improved performance, allowing users to reach coverage goals more quickly than ever before. In short, this new engine enables you to find DUT bugs faster.

For a detailed, on-site briefing on IntelliGen and the other enhancements made to Specman technology in the November 2007 "6.2" release of Specman and Incisive Enterprise Simulator, please contact your Cadence Application Engineer.

Because IntelliGen removes some limitations of Pgen and offers many generation improvements, users might have to slightly modify existing code to migrate an environment to IntelliGen. In cases where migrating the full environment is not possible, you can use both IntelliGen and Pgen together to generate different parts of the environment in a "Mixed Mode" fashion, using both generators in parallel (i.e. you can continue to use Pgen on legacy code and tune new code to IntelliGen, etc.)

1 A state where there are no valid assignments for a set of fields that satisfies the set of constraints on those fields.

2 A set of fields in a generation action that is connected by the same set of constraints

3 UVC = Universal Verification Component which is a complete verification package for verifying a particular function or interface.


 

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